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KrystalDelusion 2025-04-04 04:08:16 +13:00 committed by GitHub
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read_verilog -specify << EOT
module top(input a, b, output o);
wire c, d, e;
bb #(.SOME_PARAM(1)) bb1 (.a (a), .b (b), .o (c));
bb #(.SOME_PARAM(2)) bb2 (.a (a), .b (b), .o (d));
wb wb1 (.a (a), .b (b), .o (e));
some_mod some_inst (.a (c), .b (d), .c (e), .o (o));
endmodule
(* blackbox *)
module bb #( parameter SOME_PARAM=0 ) (input a, b, output o);
assign o = a | b;
specify
(a => o) = 1;
endspecify
endmodule
(* whitebox *)
module wb(input a, b, output o);
assign o = a ^ b;
endmodule
module some_mod(input a, b, c, output o);
assign o = a & (b | c);
endmodule
EOT
hierarchy -top top
select -assert-count 0 t:$anyseq
select -assert-count 3 =t:?b
cutpoint -blackbox
select -assert-count 3 =t:?b
select -assert-count 2 r:SOME_PARAM
select -assert-count 1 r:SOME_PARAM=1
flatten
select -assert-count 3 t:$anyseq