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Renamed techlibs/xilinx7 to techlibs/xilinx

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Clifford Wolf 2013-10-26 22:29:40 +02:00
parent 4007b41d40
commit d635f8adaa
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techlibs/xilinx/counter.v Normal file
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module counter (clk, rst, en, count);
input clk, rst, en;
output reg [3:0] count;
always @(posedge clk)
if (rst)
count <= 4'd0;
else if (en)
count <= count + 4'd1;
endmodule