diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml index bef410a3c..c758bf1f6 100644 --- a/.github/ISSUE_TEMPLATE/config.yml +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -1,11 +1,8 @@ contact_links: - - name: Discussions - url: https://github.com/YosysHQ/yosys/discussions - about: "Have a question? Ask it on our discussions page!" - - name: Community Slack - url: https://join.slack.com/t/yosyshq/shared_invite/zt-1aopkns2q-EiQ97BeQDt_pwvE41sGSuA - about: "Yosys Community Slack" + - name: Discourse + url: https://yosyshq.discourse.group + about: "Have a question? Ask it on our Discourse group!" - name: IRC Channel url: https://web.libera.chat/#yosys about: "#yosys on irc.libera.chat" - + diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index fb1fab426..a02febb3b 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -47,6 +47,7 @@ jobs: echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf echo "ENABLE_CCACHE := 1" >> Makefile.conf + echo "ENABLE_HELP_SOURCE := 1" >> Makefile.conf make -j$procs ENABLE_LTO=1 - name: Prepare docs @@ -59,7 +60,6 @@ jobs: with: name: cmd-ref-${{ github.sha }} path: | - docs/source/cmd docs/source/generated docs/source/_images docs/source/code_examples diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 22d3a94f8..bdd290189 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -225,6 +225,7 @@ jobs: run: | make config-clang echo "ENABLE_CCACHE := 1" >> Makefile.conf + echo "ENABLE_HELP_SOURCE := 1" >> Makefile.conf make -j$procs - name: Install doc prereqs diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index b01ce6b3a..d81e340aa 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -119,6 +119,11 @@ jobs: upload_wheels: name: Upload Wheels runs-on: ubuntu-latest + # Specifying a GitHub environment is optional, but strongly encouraged + environment: pypi + permissions: + # IMPORTANT: this permission is mandatory for Trusted Publishing + id-token: write needs: build_wheels steps: - uses: actions/download-artifact@v4 @@ -132,6 +137,3 @@ jobs: mv *.whl ./dist - name: Publish uses: pypa/gh-action-pypi-publish@release/v1 - with: - password: ${{ secrets.PYPI_TOKEN }} - repository-url: ${{ vars.PYPI_INDEX || 'https://upload.pypi.org/legacy/' }} diff --git a/.gitignore b/.gitignore index 7b4a1fb1e..3b77edf1f 100644 --- a/.gitignore +++ b/.gitignore @@ -1,26 +1,19 @@ +## user config +/Makefile.conf + +## build artifacts +# compiler intermediate files *.o *.d *.dwo -.*.swp *.gch *.gcda *.gcno -*~ -__pycache__ -/.cache -/.cproject -/.project -/.settings -/qtcreator.files -/qtcreator.includes -/qtcreator.config -/qtcreator.creator -/qtcreator.creator.user -/compile_commands.json -/coverage.info -/coverage_html -/Makefile.conf -/viz.js +*.so.dSYM/ + +# compiler output files +/kernel/version_*.cc +/share /yosys /yosys.exe /yosys.js @@ -36,22 +29,50 @@ __pycache__ /yosys-witness-script.py /yosys-filterlib /yosys-filterlib.exe -/kernel/*.pyh -/kernel/python_wrappers.cc -/kernel/version_*.cc -/share /yosys-win32-mxebin-* /yosys-win32-vcxsrc-* /yosysjs-* /libyosys.so + +# build directories /tests/unit/bintest/ /tests/unit/objtest/ /tests/ystests +/build /result /dist -/*.egg-info -/build -/venv + +# pyosys +/kernel/*.pyh +/kernel/python_wrappers.cc /boost /ffi +/venv /*.whl +/*.egg-info + +# yosysjs dependency +/viz.js + +# other +/coverage.info +/coverage_html + + +# these really belong in global gitignore since they're not specific to this project but rather to user tool choice +# but too many people don't have a global gitignore configured: +# https://docs.github.com/en/get-started/git-basics/ignoring-files#configuring-ignored-files-for-all-repositories-on-your-computer +__pycache__ +*~ +.*.swp +/.cache +/.vscode +/.cproject +/.project +/.settings +/qtcreator.files +/qtcreator.includes +/qtcreator.config +/qtcreator.creator +/qtcreator.creator.user +/compile_commands.json diff --git a/CHANGELOG b/CHANGELOG index d8f2f8804..6365a24e9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,9 +2,26 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.55 .. Yosys 0.56-dev +Yosys 0.56 .. Yosys 0.57-dev -------------------------- +Yosys 0.55 .. Yosys 0.56 +-------------------------- + * New commands and options + - Added "-unescape" option to "rename" pass. + - Added "-assert2cover" option to "chformal" pass. + - Added "linecoverage" pass to generate lcov report from selection. + - Added "opt_hier" pass to enable hierarchical optimization. + - Added "-hieropt" option to "synth" pass. + - Added "-expect-return", "-err-grep" and "-suffix" options + to "bugpoint" pass. + - Added "raise_error" dev pass. + + * Various + - Added groups to command reference documentation. + - Added bugpoint guide to documentation. + - verific: correctly reset Verific flags after import. + Yosys 0.54 .. Yosys 0.55 -------------------------- * Various diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 6c4376cc4..74f9ab10d 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -19,14 +19,14 @@ much easier for someone to respond and help. ### Bug reports -Before you submit an issue, please have a search of the existing issues in case -one already exists. Making sure that you have a minimal, complete and -verifiable example (MVCE) is a great way to quickly check an existing issue -against a new one. Stack overflow has a guide on [how to create an -MVCE](https://stackoverflow.com/help/minimal-reproducible-example). The -[`bugpoint` -command](https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/bugpoint.html) -in Yosys can be helpful for this process. +Before you submit an issue, please check out the [how-to guide for +`bugpoint`](https://yosys.readthedocs.io/en/latest/using_yosys/bugpoint.html). +This guide will take you through the process of using the [`bugpoint` +command](https://yosys.readthedocs.io/en/latest/cmd/bugpoint.html) in Yosys to +produce a [minimal, complete and verifiable +example](https://stackoverflow.com/help/minimal-reproducible-example) (MVCE). +Providing an MVCE with your bug report drastically increases the likelihood that +someone will be able to help resolve your issue. # Using pull requests diff --git a/Makefile b/Makefile index b7928f33a..b27a45424 100644 --- a/Makefile +++ b/Makefile @@ -24,6 +24,7 @@ ENABLE_VERIFIC_LIBERTY := 0 ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 ENABLE_ZLIB := 1 +ENABLE_HELP_SOURCE := 0 # python wrappers ENABLE_PYOSYS := 0 @@ -109,18 +110,16 @@ PLUGIN_LINKFLAGS += -L"$(LIBDIR)" PLUGIN_LIBS := -lyosys_exe endif +ifeq ($(ENABLE_HELP_SOURCE),1) +CXXFLAGS += -DYOSYS_ENABLE_HELP_SOURCE +endif + PKG_CONFIG ?= pkg-config SED ?= sed BISON ?= bison STRIP ?= strip AWK ?= awk -ifneq ($(shell :; command -v rsync),) -RSYNC_CP ?= rsync -rc -else -RSYNC_CP ?= cp -ru -endif - ifeq ($(OS), Darwin) PLUGIN_LINKFLAGS += -undefined dynamic_lookup LINKFLAGS += -rdynamic @@ -160,7 +159,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.55+0 +YOSYS_VER := 0.56+0 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) @@ -183,7 +182,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 60f126c.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9c447ad.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) @@ -532,7 +531,6 @@ LIBS_VERIFIC += -Wl,--whole-archive $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VE endif endif - ifeq ($(ENABLE_COVER),1) CXXFLAGS += -DYOSYS_ENABLE_COVER endif @@ -627,12 +625,14 @@ endif $(eval $(call add_include_file,libs/sha1/sha1.h)) $(eval $(call add_include_file,libs/json11/json11.hpp)) $(eval $(call add_include_file,passes/fsm/fsmdata.h)) +$(eval $(call add_include_file,passes/techmap/libparse.h)) $(eval $(call add_include_file,frontends/ast/ast.h)) $(eval $(call add_include_file,frontends/ast/ast_binding.h)) $(eval $(call add_include_file,frontends/blif/blifparse.h)) $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/io.o kernel/gzip.o +OBJS += kernel/log_help.o OBJS += kernel/binding.o kernel/tclapi.o OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o OBJS += kernel/drivertools.o kernel/functional.o @@ -867,6 +867,7 @@ MK_TEST_DIRS += tests/arch/nexus MK_TEST_DIRS += tests/arch/quicklogic/pp3 MK_TEST_DIRS += tests/arch/quicklogic/qlf_k6n10f MK_TEST_DIRS += tests/arch/xilinx +MK_TEST_DIRS += tests/bugpoint MK_TEST_DIRS += tests/opt MK_TEST_DIRS += tests/sat MK_TEST_DIRS += tests/sim @@ -980,6 +981,12 @@ unit-test: libyosys.so clean-unit-test: @$(MAKE) -C $(UNITESTPATH) clean +install-dev: $(PROGRAM_PREFIX)yosys-config share + $(INSTALL_SUDO) mkdir -p $(DESTDIR)$(BINDIR) + $(INSTALL_SUDO) cp $(PROGRAM_PREFIX)yosys-config $(DESTDIR)$(BINDIR) + $(INSTALL_SUDO) mkdir -p $(DESTDIR)$(DATDIR) + $(INSTALL_SUDO) cp -r share/. $(DESTDIR)$(DATDIR)/. + install: $(TARGETS) $(EXTRA_TARGETS) $(INSTALL_SUDO) mkdir -p $(DESTDIR)$(BINDIR) $(INSTALL_SUDO) cp $(filter-out libyosys.so,$(TARGETS)) $(DESTDIR)$(BINDIR) @@ -1027,19 +1034,8 @@ ifeq ($(ENABLE_PYOSYS),1) endif endif -# also others, but so long as it doesn't fail this is enough to know we tried -docs/source/cmd/abc.rst: $(TARGETS) $(EXTRA_TARGETS) - $(Q) mkdir -p docs/source/cmd - $(Q) mkdir -p temp/docs/source/cmd - $(Q) cd temp && ./../$(PROGRAM_PREFIX)yosys -p 'help -write-rst-command-reference-manual' - $(Q) $(RSYNC_CP) temp/docs/source/cmd docs/source - $(Q) rm -rf temp -docs/source/cell/word_add.rst: $(TARGETS) $(EXTRA_TARGETS) - $(Q) mkdir -p docs/source/cell - $(Q) mkdir -p temp/docs/source/cell - $(Q) cd temp && ./../$(PROGRAM_PREFIX)yosys -p 'help -write-rst-cells-manual' - $(Q) $(RSYNC_CP) temp/docs/source/cell docs/source - $(Q) rm -rf temp +docs/source/generated/cmds.json: docs/source/generated $(TARGETS) $(EXTRA_TARGETS) + $(Q) ./$(PROGRAM_PREFIX)yosys -p 'help -dump-cmds-json $@' docs/source/generated/cells.json: docs/source/generated $(TARGETS) $(EXTRA_TARGETS) $(Q) ./$(PROGRAM_PREFIX)yosys -p 'help -dump-cells-json $@' @@ -1056,6 +1052,15 @@ docs/source/generated/functional/rosette.diff: backends/functional/smtlib.cc bac PHONY: docs/gen/functional_ir docs/gen/functional_ir: docs/source/generated/functional/smtlib.cc docs/source/generated/functional/rosette.diff +docs/source/generated/%.log: docs/source/generated $(TARGETS) $(EXTRA_TARGETS) + $(Q) ./$(PROGRAM_PREFIX)yosys -qQT -h '$*' -l $@ + +docs/source/generated/chformal.cc: passes/cmds/chformal.cc docs/source/generated + $(Q) cp $< $@ + +PHONY: docs/gen/chformal +docs/gen/chformal: docs/source/generated/chformal.log docs/source/generated/chformal.cc + PHONY: docs/gen docs/usage docs/reqs docs/gen: $(TARGETS) $(Q) $(MAKE) -C docs gen @@ -1091,7 +1096,7 @@ docs/reqs: $(Q) $(MAKE) -C docs reqs .PHONY: docs/prep -docs/prep: docs/source/cmd/abc.rst docs/source/generated/cells.json docs/gen docs/usage docs/gen/functional_ir +docs/prep: docs/source/generated/cells.json docs/source/generated/cmds.json docs/gen docs/usage docs/gen/functional_ir docs/gen/chformal DOC_TARGET ?= html docs: docs/prep @@ -1115,7 +1120,7 @@ clean: rm -f tests/tools/cmp_tbdata rm -f $(addsuffix /run-test.mk,$(MK_TEST_DIRS)) -$(MAKE) -C docs clean - rm -rf docs/source/cmd docs/util/__pycache__ + rm -rf docs/util/__pycache__ rm -f *.whl rm -f libyosys.so @@ -1222,5 +1227,5 @@ echo-cxx: FORCE: -.PHONY: all top-all abc test install install-abc docs clean mrproper qtcreator coverage vcxsrc +.PHONY: all top-all abc test install-dev install install-abc docs clean mrproper qtcreator coverage vcxsrc .PHONY: config-clean config-clang config-gcc config-gcc-static config-gprof config-sudo diff --git a/README.md b/README.md index 71d47d76c..e5b8d1072 100644 --- a/README.md +++ b/README.md @@ -25,6 +25,9 @@ Web Site and Other Resources More information and documentation can be found on the Yosys web site: - https://yosyshq.net/yosys/ +If you have any Yosys-related questions, please post them on the Discourse group: +- https://yosyshq.discourse.group + Documentation from this repository is automatically built and available on Read the Docs: - https://yosyshq.readthedocs.io/projects/yosys @@ -34,6 +37,9 @@ verification front-end for Yosys, SBY: - https://yosyshq.readthedocs.io/projects/sby/ - https://github.com/YosysHQ/sby +The Yosys blog has news and articles from users: +- https://blog.yosyshq.com + Installation ============ @@ -242,7 +248,7 @@ Note that there is no need to build the manual if you just want to read it. Simply visit https://yosys.readthedocs.io/en/latest/ instead. In addition to those packages listed above for building Yosys from source, the -following are used for building the website: +following are used for building the website: $ sudo apt install pdf2svg faketime @@ -258,7 +264,7 @@ build process for the website. Or, run the following: Or for MacOS, using homebrew: $ brew install basictex - $ sudo tlmgr update --self + $ sudo tlmgr update --self $ sudo tlmgr install collection-latexextra latexmk tex-gyre The Python package, Sphinx, is needed along with those listed in @@ -268,5 +274,13 @@ The Python package, Sphinx, is needed along with those listed in From the root of the repository, run `make docs`. This will build/rebuild yosys as necessary before generating the website documentation from the yosys help -commands. To build for pdf instead of html, call +commands. To build for pdf instead of html, call `make docs DOC_TARGET=latexpdf`. + +It is recommended to use the `ENABLE_HELP_SOURCE` make option for Yosys builds +that will be used to build the documentation. This option enables source +location tracking for passes and improves the command reference through grouping +related commands and allowing for the documentation to link to the corresponding +source files. Without this, a warning will be raised during the Sphinx build +about `Found commands assigned to group unknown` and `make docs` is configured +to fail on warnings by default. diff --git a/abc b/abc index e55d316cc..fa7fa163d 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit e55d316cc9a7f72a84a76eda555aa6ec083c9d0d +Subproject commit fa7fa163dacdf81bdcb72b2d2713fbe9984b62bb diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index ceb805dcb..e4254f85a 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -1223,6 +1223,7 @@ struct FirrtlBackend : public Backend { Pass::call(design, "demuxmap"); Pass::call(design, "bwmuxmap"); + used_names.clear(); namecache.clear(); autoid_counter = 0; @@ -1262,6 +1263,7 @@ struct FirrtlBackend : public Backend { } } + used_names.clear(); namecache.clear(); autoid_counter = 0; } diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index a9dfd0c70..42d6c2b95 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -116,7 +116,9 @@ struct MemContentsTest { struct FunctionalTestGeneric : public Pass { - FunctionalTestGeneric() : Pass("test_generic", "test the generic compute graph") {} + FunctionalTestGeneric() : Pass("test_generic", "test the generic compute graph") { + internal(); + } void help() override { diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 997740a7c..070df1543 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -28,12 +28,71 @@ #include "kernel/ff.h" #include "kernel/mem.h" #include "kernel/fmt.h" +#include "backends/verilog/verilog_backend.h" #include #include #include #include USING_YOSYS_NAMESPACE + +using namespace VERILOG_BACKEND; + +const pool VERILOG_BACKEND::verilog_keywords() { + static const pool res = { + // IEEE 1800-2017 Annex B + "accept_on", "alias", "always", "always_comb", "always_ff", "always_latch", "and", "assert", "assign", "assume", "automatic", "before", + "begin", "bind", "bins", "binsof", "bit", "break", "buf", "bufif0", "bufif1", "byte", "case", "casex", "casez", "cell", "chandle", + "checker", "class", "clocking", "cmos", "config", "const", "constraint", "context", "continue", "cover", "covergroup", "coverpoint", + "cross", "deassign", "default", "defparam", "design", "disable", "dist", "do", "edge", "else", "end", "endcase", "endchecker", + "endclass", "endclocking", "endconfig", "endfunction", "endgenerate", "endgroup", "endinterface", "endmodule", "endpackage", + "endprimitive", "endprogram", "endproperty", "endsequence", "endspecify", "endtable", "endtask", "enum", "event", "eventually", + "expect", "export", "extends", "extern", "final", "first_match", "for", "force", "foreach", "forever", "fork", "forkjoin", "function", + "generate", "genvar", "global", "highz0", "highz1", "if", "iff", "ifnone", "ignore_bins", "illegal_bins", "implements", "implies", + "import", "incdir", "include", "initial", "inout", "input", "inside", "instance", "int", "integer", "interconnect", "interface", + "intersect", "join", "join_any", "join_none", "large", "let", "liblist", "library", "local", "localparam", "logic", "longint", + "macromodule", "matches", "medium", "modport", "module", "nand", "negedge", "nettype", "new", "nexttime", "nmos", "nor", + "noshowcancelled", "not", "notif0", "notif1", "null", "or", "output", "package", "packed", "parameter", "pmos", "posedge", "primitive", + "priority", "program", "property", "protected", "pull0", "pull1", "pulldown", "pullup", "pulsestyle_ondetect", "pulsestyle_onevent", + "pure", "rand", "randc", "randcase", "randsequence", "rcmos", "real", "realtime", "ref", "reg", "reject_on", "release", "repeat", + "restrict", "return", "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "s_always", "s_eventually", "s_nexttime", "s_until", + "s_until_with", "scalared", "sequence", "shortint", "shortreal", "showcancelled", "signed", "small", "soft", "solve", "specify", + "specparam", "static", "string", "strong", "strong0", "strong1", "struct", "super", "supply0", "supply1", "sync_accept_on", + "sync_reject_on", "table", "tagged", "task", "this", "throughout", "time", "timeprecision", "timeunit", "tran", "tranif0", "tranif1", + "tri", "tri0", "tri1", "triand", "trior", "trireg", "type", "typedef", "union", "unique", "unique0", "unsigned", "until", "until_with", + "untyped", "use", "uwire", "var", "vectored", "virtual", "void", "wait", "wait_order", "wand", "weak", "weak0", "weak1", "while", + "wildcard", "wire", "with", "within", "wor", "xnor", "xor", + }; + return res; +} + +bool VERILOG_BACKEND::char_is_verilog_escaped(char c) { + if ('0' <= c && c <= '9') + return false; + if ('a' <= c && c <= 'z') + return false; + if ('A' <= c && c <= 'Z') + return false; + if (c == '_') + return false; + + return true; +} + +bool VERILOG_BACKEND::id_is_verilog_escaped(const std::string &str) { + if ('0' <= str[0] && str[0] <= '9') + return true; + + for (int i = 0; str[i]; i++) + if (char_is_verilog_escaped(str[i])) + return true; + + if (verilog_keywords().count(str)) + return true; + + return false; +} + PRIVATE_NAMESPACE_BEGIN bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs, noparallelcase; @@ -105,7 +164,6 @@ std::string next_auto_id() std::string id(RTLIL::IdString internal_id, bool may_rename = true) { const char *str = internal_id.c_str(); - bool do_escape = false; if (may_rename && auto_name_map.count(internal_id) != 0) return stringf("%s_%0*d_", auto_prefix.c_str(), auto_name_digits, auto_name_offset + auto_name_map[internal_id]); @@ -113,51 +171,7 @@ std::string id(RTLIL::IdString internal_id, bool may_rename = true) if (*str == '\\') str++; - if ('0' <= *str && *str <= '9') - do_escape = true; - - for (int i = 0; str[i]; i++) - { - if ('0' <= str[i] && str[i] <= '9') - continue; - if ('a' <= str[i] && str[i] <= 'z') - continue; - if ('A' <= str[i] && str[i] <= 'Z') - continue; - if (str[i] == '_') - continue; - do_escape = true; - break; - } - - static const pool keywords = { - // IEEE 1800-2017 Annex B - "accept_on", "alias", "always", "always_comb", "always_ff", "always_latch", "and", "assert", "assign", "assume", "automatic", "before", - "begin", "bind", "bins", "binsof", "bit", "break", "buf", "bufif0", "bufif1", "byte", "case", "casex", "casez", "cell", "chandle", - "checker", "class", "clocking", "cmos", "config", "const", "constraint", "context", "continue", "cover", "covergroup", "coverpoint", - "cross", "deassign", "default", "defparam", "design", "disable", "dist", "do", "edge", "else", "end", "endcase", "endchecker", - "endclass", "endclocking", "endconfig", "endfunction", "endgenerate", "endgroup", "endinterface", "endmodule", "endpackage", - "endprimitive", "endprogram", "endproperty", "endsequence", "endspecify", "endtable", "endtask", "enum", "event", "eventually", - "expect", "export", "extends", "extern", "final", "first_match", "for", "force", "foreach", "forever", "fork", "forkjoin", "function", - "generate", "genvar", "global", "highz0", "highz1", "if", "iff", "ifnone", "ignore_bins", "illegal_bins", "implements", "implies", - "import", "incdir", "include", "initial", "inout", "input", "inside", "instance", "int", "integer", "interconnect", "interface", - "intersect", "join", "join_any", "join_none", "large", "let", "liblist", "library", "local", "localparam", "logic", "longint", - "macromodule", "matches", "medium", "modport", "module", "nand", "negedge", "nettype", "new", "nexttime", "nmos", "nor", - "noshowcancelled", "not", "notif0", "notif1", "null", "or", "output", "package", "packed", "parameter", "pmos", "posedge", "primitive", - "priority", "program", "property", "protected", "pull0", "pull1", "pulldown", "pullup", "pulsestyle_ondetect", "pulsestyle_onevent", - "pure", "rand", "randc", "randcase", "randsequence", "rcmos", "real", "realtime", "ref", "reg", "reject_on", "release", "repeat", - "restrict", "return", "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "s_always", "s_eventually", "s_nexttime", "s_until", - "s_until_with", "scalared", "sequence", "shortint", "shortreal", "showcancelled", "signed", "small", "soft", "solve", "specify", - "specparam", "static", "string", "strong", "strong0", "strong1", "struct", "super", "supply0", "supply1", "sync_accept_on", - "sync_reject_on", "table", "tagged", "task", "this", "throughout", "time", "timeprecision", "timeunit", "tran", "tranif0", "tranif1", - "tri", "tri0", "tri1", "triand", "trior", "trireg", "type", "typedef", "union", "unique", "unique0", "unsigned", "until", "until_with", - "untyped", "use", "uwire", "var", "vectored", "virtual", "void", "wait", "wait_order", "wand", "weak", "weak0", "weak1", "while", - "wildcard", "wire", "with", "within", "wor", "xnor", "xor", - }; - if (keywords.count(str)) - do_escape = true; - - if (do_escape) + if (id_is_verilog_escaped(str)) return "\\" + std::string(str) + " "; return std::string(str); } @@ -1149,9 +1163,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); - f << stringf(cell->type == ID($_AOI3_) ? " & " : " | "); + f << (cell->type == ID($_AOI3_) ? " & " : " | "); dump_cell_expr_port(f, cell, "B", false); - f << stringf(cell->type == ID($_AOI3_) ? ") |" : ") &"); + f << (cell->type == ID($_AOI3_) ? ") |" : ") &"); dump_attributes(f, "", cell->attributes, " "); f << stringf(" "); dump_cell_expr_port(f, cell, "C", false); @@ -1164,13 +1178,13 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); - f << stringf(cell->type == ID($_AOI4_) ? " & " : " | "); + f << (cell->type == ID($_AOI4_) ? " & " : " | "); dump_cell_expr_port(f, cell, "B", false); - f << stringf(cell->type == ID($_AOI4_) ? ") |" : ") &"); + f << (cell->type == ID($_AOI4_) ? ") |" : ") &"); dump_attributes(f, "", cell->attributes, " "); f << stringf(" ("); dump_cell_expr_port(f, cell, "C", false); - f << stringf(cell->type == ID($_AOI4_) ? " & " : " | "); + f << (cell->type == ID($_AOI4_) ? " & " : " | "); dump_cell_expr_port(f, cell, "D", false); f << stringf("));\n"); return true; @@ -1381,10 +1395,10 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) int s_width = cell->getPort(ID::S).size(); std::string func_name = cellname(cell); - f << stringf("%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); - f << stringf("%s" " input [%d:0] a;\n", indent.c_str(), width-1); - f << stringf("%s" " input [%d:0] b;\n", indent.c_str(), s_width*width-1); - f << stringf("%s" " input [%d:0] s;\n", indent.c_str(), s_width-1); + f << stringf("%s" "function [%d:0] %s;\n", indent, width-1, func_name); + f << stringf("%s" " input [%d:0] a;\n", indent, width-1); + f << stringf("%s" " input [%d:0] b;\n", indent, s_width*width-1); + f << stringf("%s" " input [%d:0] s;\n", indent, s_width-1); dump_attributes(f, indent + " ", cell->attributes); if (noparallelcase) @@ -1393,7 +1407,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (!noattr) f << stringf("%s" " (* parallel_case *)\n", indent.c_str()); f << stringf("%s" " casez (s)", indent.c_str()); - f << stringf(noattr ? " // synopsys parallel_case\n" : "\n"); + f << (noattr ? " // synopsys parallel_case\n" : "\n"); } for (int i = 0; i < s_width; i++) @@ -2598,7 +2612,7 @@ struct VerilogBackend : public Backend { Pass::call(design, "clean_zerowidth"); log_pop(); - design->sort(); + design->sort_modules(); *f << stringf("/* Generated by %s */\n", yosys_maybe_version()); @@ -2611,6 +2625,7 @@ struct VerilogBackend : public Backend { continue; } log("Dumping module `%s'.\n", module->name.c_str()); + module->sort(); dump_module(*f, "", module); } diff --git a/backends/verilog/verilog_backend.h b/backends/verilog/verilog_backend.h new file mode 100644 index 000000000..7e550a37c --- /dev/null +++ b/backends/verilog/verilog_backend.h @@ -0,0 +1,39 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * --- + * + * A simple and straightforward Verilog backend. + * + */ + +#ifndef VERILOG_BACKEND_H +#define VERILOG_BACKEND_H + +#include + +YOSYS_NAMESPACE_BEGIN +namespace VERILOG_BACKEND { + + const pool verilog_keywords(); + bool char_is_verilog_escaped(char c); + bool id_is_verilog_escaped(const std::string &str); + +}; /* namespace VERILOG_BACKEND */ +YOSYS_NAMESPACE_END + +#endif /* VERILOG_BACKEND_H */ diff --git a/docs/.gitignore b/docs/.gitignore index 65bbcdeae..09bb59048 100644 --- a/docs/.gitignore +++ b/docs/.gitignore @@ -1,5 +1,4 @@ /build/ -/source/cmd /source/generated /source/_images/**/*.log /source/_images/**/*.aux diff --git a/docs/Makefile b/docs/Makefile index a8874bb83..fb3e03b79 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -47,7 +47,7 @@ help: .PHONY: clean clean: clean-examples rm -rf $(BUILDDIR)/* - rm -rf source/cmd util/__pycache__ + rm -rf util/__pycache__ rm -rf source/generated $(MAKE) -C source/_images clean diff --git a/docs/source/_static/custom.css b/docs/source/_static/custom.css index b08194c05..60faf6812 100644 --- a/docs/source/_static/custom.css +++ b/docs/source/_static/custom.css @@ -18,3 +18,8 @@ .literal-block-wrapper .code-block-caption .caption-number { padding-right: 0.5em } + +/* Don't double shrink text in a literal in an optionlist */ +kbd .option>.literal { + font-size: revert; +} diff --git a/docs/source/appendix/auxlibs.rst b/docs/source/appendix/auxlibs.rst index 8c78ed6b3..192ac0944 100644 --- a/docs/source/appendix/auxlibs.rst +++ b/docs/source/appendix/auxlibs.rst @@ -29,8 +29,7 @@ ezSAT The files in ``libs/ezsat`` provide a library for simplifying generating CNF formulas for SAT solvers. It also contains bindings of MiniSAT. The ezSAT -library is written by C. Wolf. It is used by the `sat` pass (see -:doc:`/cmd/sat`). +library is written by C. Wolf. It is used by the `sat` pass. fst --- @@ -78,4 +77,4 @@ SubCircuit The files in ``libs/subcircuit`` provide a library for solving the subcircuit isomorphism problem. It is written by C. Wolf and based on the Ullmann Subgraph Isomorphism Algorithm :cite:p:`UllmannSubgraphIsomorphism`. It is used by the -extract pass (see :doc:`../cmd/extract`). +`extract` pass. diff --git a/docs/source/cmd/index_backends.rst b/docs/source/cmd/index_backends.rst new file mode 100644 index 000000000..373c26def --- /dev/null +++ b/docs/source/cmd/index_backends.rst @@ -0,0 +1,5 @@ +Writing output files +-------------------- + +.. autocmdgroup:: backends + :members: diff --git a/docs/source/cmd/index_formal.rst b/docs/source/cmd/index_formal.rst new file mode 100644 index 000000000..b8b134c17 --- /dev/null +++ b/docs/source/cmd/index_formal.rst @@ -0,0 +1,5 @@ +Formal verification +------------------- + +.. autocmdgroup:: formal + :members: diff --git a/docs/source/cmd/index_frontends.rst b/docs/source/cmd/index_frontends.rst new file mode 100644 index 000000000..b64fdc9b9 --- /dev/null +++ b/docs/source/cmd/index_frontends.rst @@ -0,0 +1,5 @@ +Reading input files +------------------- + +.. autocmdgroup:: frontends + :members: diff --git a/docs/source/cmd/index_internal.rst b/docs/source/cmd/index_internal.rst new file mode 100644 index 000000000..bfb369dde --- /dev/null +++ b/docs/source/cmd/index_internal.rst @@ -0,0 +1,152 @@ +Internal commands for developers +-------------------------------- + +.. autocmdgroup:: internal + :members: + +Writing command help +-------------------- + +- use `chformal` as an example +- generated help content below + +.. _chformal autocmd: + +.. autocmd:: chformal + :noindex: + +The ``formatted_help()`` method +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- ``PrettyHelp::get_current()`` +- ``PrettyHelp::set_group()`` + + + used with ``.. autocmdgroup:: `` + + can assign group and return false + + if no group is set, will try to use ``source_location`` and assign group + from path to source file + +- return value + + + true means help content added to current ``PrettyHelp`` + + false to use ``Pass::help()`` + +- adding content + + + help content is a list of ``ContentListing`` nodes, each one having a type, + body, and its own list of children ``ContentListing``\ s + + ``PrettyHelp::get_root()`` returns the root ``ContentListing`` (``type="root"``) + + ``ContentListing::{usage, option, codeblock, paragraph}`` each add a + ``ContentListing`` to the current node, with type the same as the method + + * the first argument is the body of the new node + * ``usage`` shows how to call the command (i.e. its "signature") + * ``paragraph`` content is formatted as a paragraph of text with line breaks + added automatically + * ``codeblock`` content is displayed verbatim, use line breaks as desired; + takes an optional ``language`` argument for assigning the language in RST + output for code syntax highlighting (use ``yoscrypt`` for yosys script + syntax highlighting) + * ``option`` lists a single option for the command, usually starting with a + dash (``-``); takes an optional second argument which adds a paragraph + node as a means of description + + + ``ContentListing::open_usage`` creates and returns a new usage node, can be + used to e.g. add text/options specific to a given usage of the command + + ``ContentListing::open_option`` creates and returns a new option node, can + be used to e.g. add multiple paragraphs to an option's description + + paragraphs are treated as raw RST, allowing for inline formatting and + references as if it were written in the RST file itself + +.. literalinclude:: /generated/chformal.cc + :language: c++ + :start-at: bool formatted_help() + :end-before: void execute + :caption: ``ChformalPass::formatted_help()`` from :file:`passes/cmds/chformal.cc` + +Dumping command help to json +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- `help -dump-cells-json cmds.json` + + + generates a ``ContentListing`` for each command registered in Yosys + + tries to parse unformatted ``Pass::help()`` output if + ``Pass::formatted_help()`` is unimplemented or returns false + + * if a line starts with four spaces followed by the name of the command then + a space, it is parsed as a signature (usage node) + * if a line is indented and starts with a dash (``-``), it is parsed as an + option + * anything else is parsed as a codeblock and added to either the root node + or the current option depending on the indentation + + + dictionary of command name to ``ContentListing`` + + * uses ``ContentListing::to_json()`` recursively for each node in root + * root node used for source location of class definition + * includes flags set during pass constructor (e.g. ``experimental_flag`` set + by ``Pass::experimental()``) + * also title (``short_help`` argument in ``Pass::Pass``), group, and class + name + + + dictionary of group name to list of commands in that group + +- used by sphinx autodoc to generate help content + +.. literalinclude:: /generated/cmds.json + :language: json + :start-at: "chformal": { + :end-before: "chparam": { + :caption: `chformal` in generated :file:`cmds.json` + +.. note:: Synthesis command scripts are special cased + + If the final block of help output starts with the string `"The following + commands are executed by this synthesis command:\n"`, then the rest of the + code block is formatted as ``yoscrypt`` (e.g. `synth_ice40`). The caveat + here is that if the ``script()`` calls ``run()`` on any commands *prior* to + the first ``check_label`` then the auto detection will break and revert to + unformatted code (e.g. `synth_fabulous`). + +Command line rendering +~~~~~~~~~~~~~~~~~~~~~~ + +- if ``Pass::formatted_help()`` returns true, will call + ``PrettyHelp::log_help()`` + + + traverse over the children of the root node and render as plain text + + effectively the reverse of converting unformatted ``Pass::help()`` text + + lines are broken at 80 characters while maintaining indentation (controlled + by ``MAX_LINE_LEN`` in :file:`kernel/log_help.cc`) + + each line is broken into words separated by spaces, if a given word starts + and ends with backticks they will be stripped + +- if it returns false it will call ``Pass::help()`` which should call ``log()`` + directly to print and format help text + + + if ``Pass::help()`` is not overridden then a default message about missing + help will be displayed + +.. literalinclude:: /generated/chformal.log + :lines: 2- + +RST generated from autocmd +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- below is the raw RST output from ``autocmd`` (``YosysCmdDocumenter`` class in + :file:`docs/util/cmd_documenter.py`) for `chformal` command +- heading will be rendered as a subheading of the most recent heading (see + `chformal autocmd`_ above rendered under `Writing command help`_) +- ``.. cmd:def:: `` line is indexed for cross references with ``:cmd:ref:`` + directive (`chformal autocmd`_ above uses ``:noindex:`` option so that + `chformal` still links to the correct location) + + + ``:title:`` option controls text that appears when hovering over the + `chformal` link + +- commands with warning flags (experimental or internal) add a ``.. warning`` + block before any of the help content +- if a command has no ``source_location`` the ``.. note`` at the bottom will + instead link to :doc:`/cmd/index_other` + +.. autocmd_rst:: chformal diff --git a/docs/source/cmd/index_kernel.rst b/docs/source/cmd/index_kernel.rst new file mode 100644 index 000000000..c6891b5e5 --- /dev/null +++ b/docs/source/cmd/index_kernel.rst @@ -0,0 +1,5 @@ +Yosys kernel commands +--------------------- + +.. autocmdgroup:: kernel + :members: diff --git a/docs/source/cmd/index_other.rst b/docs/source/cmd/index_other.rst new file mode 100644 index 000000000..540cf9e49 --- /dev/null +++ b/docs/source/cmd/index_other.rst @@ -0,0 +1,9 @@ +:orphan: + +Other commands +============== + +Unknown source location + +.. autocmdgroup:: unknown + :members: diff --git a/docs/source/cmd/index_passes.rst b/docs/source/cmd/index_passes.rst new file mode 100644 index 000000000..b652be004 --- /dev/null +++ b/docs/source/cmd/index_passes.rst @@ -0,0 +1,14 @@ +Passes +------ + +.. toctree:: + :maxdepth: 2 + :glob: + + /cmd/index_passes_hierarchy + /cmd/index_passes_proc + /cmd/index_passes_fsm + /cmd/index_passes_memory + /cmd/index_passes_opt + /cmd/index_passes_techmap + /cmd/index_passes_* diff --git a/docs/source/cmd/index_passes_cmds.rst b/docs/source/cmd/index_passes_cmds.rst new file mode 100644 index 000000000..d7b448f07 --- /dev/null +++ b/docs/source/cmd/index_passes_cmds.rst @@ -0,0 +1,5 @@ +Design modification +------------------- + +.. autocmdgroup:: passes/cmds + :members: diff --git a/docs/source/cmd/index_passes_equiv.rst b/docs/source/cmd/index_passes_equiv.rst new file mode 100644 index 000000000..6ed2c3c18 --- /dev/null +++ b/docs/source/cmd/index_passes_equiv.rst @@ -0,0 +1,5 @@ +Equivalence checking +-------------------- + +.. autocmdgroup:: passes/equiv + :members: diff --git a/docs/source/cmd/index_passes_fsm.rst b/docs/source/cmd/index_passes_fsm.rst new file mode 100644 index 000000000..43af5dce6 --- /dev/null +++ b/docs/source/cmd/index_passes_fsm.rst @@ -0,0 +1,5 @@ +FSM handling +------------ + +.. autocmdgroup:: passes/fsm + :members: diff --git a/docs/source/cmd/index_passes_hierarchy.rst b/docs/source/cmd/index_passes_hierarchy.rst new file mode 100644 index 000000000..27a0faeb7 --- /dev/null +++ b/docs/source/cmd/index_passes_hierarchy.rst @@ -0,0 +1,5 @@ +Working with hierarchy +---------------------- + +.. autocmdgroup:: passes/hierarchy + :members: diff --git a/docs/source/cmd/index_passes_memory.rst b/docs/source/cmd/index_passes_memory.rst new file mode 100644 index 000000000..b4edb88e7 --- /dev/null +++ b/docs/source/cmd/index_passes_memory.rst @@ -0,0 +1,5 @@ +Memory handling +--------------- + +.. autocmdgroup:: passes/memory + :members: diff --git a/docs/source/cmd/index_passes_opt.rst b/docs/source/cmd/index_passes_opt.rst new file mode 100644 index 000000000..ddeb5ce10 --- /dev/null +++ b/docs/source/cmd/index_passes_opt.rst @@ -0,0 +1,5 @@ +Optimization passes +------------------- + +.. autocmdgroup:: passes/opt + :members: diff --git a/docs/source/cmd/index_passes_proc.rst b/docs/source/cmd/index_passes_proc.rst new file mode 100644 index 000000000..1ad8d85b4 --- /dev/null +++ b/docs/source/cmd/index_passes_proc.rst @@ -0,0 +1,5 @@ +Converting process blocks +------------------------- + +.. autocmdgroup:: passes/proc + :members: diff --git a/docs/source/cmd/index_passes_sat.rst b/docs/source/cmd/index_passes_sat.rst new file mode 100644 index 000000000..a2571fedb --- /dev/null +++ b/docs/source/cmd/index_passes_sat.rst @@ -0,0 +1,5 @@ +Simulating circuits +------------------- + +.. autocmdgroup:: passes/sat + :members: diff --git a/docs/source/cmd/index_passes_status.rst b/docs/source/cmd/index_passes_status.rst new file mode 100644 index 000000000..a157ed840 --- /dev/null +++ b/docs/source/cmd/index_passes_status.rst @@ -0,0 +1,5 @@ +Design status +------------- + +.. autocmdgroup:: passes/status + :members: diff --git a/docs/source/cmd/index_passes_techmap.rst b/docs/source/cmd/index_passes_techmap.rst new file mode 100644 index 000000000..1682cd181 --- /dev/null +++ b/docs/source/cmd/index_passes_techmap.rst @@ -0,0 +1,7 @@ +Technology mapping +------------------ + +.. seealso:: :doc:`/cmd/index_techlibs` + +.. autocmdgroup:: passes/techmap + :members: diff --git a/docs/source/cmd/index_techlibs.rst b/docs/source/cmd/index_techlibs.rst new file mode 100644 index 000000000..043620a3b --- /dev/null +++ b/docs/source/cmd/index_techlibs.rst @@ -0,0 +1,11 @@ +Technology libraries +==================== + +Listed in alphabetical order. + +.. toctree:: + :maxdepth: 2 + :glob: + + /cmd/index_techlibs_common + /cmd/index_techlibs_* diff --git a/docs/source/cmd/index_techlibs_achronix.rst b/docs/source/cmd/index_techlibs_achronix.rst new file mode 100644 index 000000000..d4d96d24a --- /dev/null +++ b/docs/source/cmd/index_techlibs_achronix.rst @@ -0,0 +1,5 @@ +Achronix +------------------ + +.. autocmdgroup:: techlibs/achronix + :members: diff --git a/docs/source/cmd/index_techlibs_anlogic.rst b/docs/source/cmd/index_techlibs_anlogic.rst new file mode 100644 index 000000000..8a2e6b577 --- /dev/null +++ b/docs/source/cmd/index_techlibs_anlogic.rst @@ -0,0 +1,5 @@ +Anlogic +------------------ + +.. autocmdgroup:: techlibs/anlogic + :members: diff --git a/docs/source/cmd/index_techlibs_common.rst b/docs/source/cmd/index_techlibs_common.rst new file mode 100644 index 000000000..532f4291e --- /dev/null +++ b/docs/source/cmd/index_techlibs_common.rst @@ -0,0 +1,5 @@ +Generic +------------------ + +.. autocmdgroup:: techlibs/common + :members: diff --git a/docs/source/cmd/index_techlibs_coolrunner2.rst b/docs/source/cmd/index_techlibs_coolrunner2.rst new file mode 100644 index 000000000..23d91a500 --- /dev/null +++ b/docs/source/cmd/index_techlibs_coolrunner2.rst @@ -0,0 +1,5 @@ +CoolRunner-II +------------------ + +.. autocmdgroup:: techlibs/coolrunner2 + :members: diff --git a/docs/source/cmd/index_techlibs_easic.rst b/docs/source/cmd/index_techlibs_easic.rst new file mode 100644 index 000000000..c6398ddf3 --- /dev/null +++ b/docs/source/cmd/index_techlibs_easic.rst @@ -0,0 +1,5 @@ +eASIC +------------------ + +.. autocmdgroup:: techlibs/easic + :members: diff --git a/docs/source/cmd/index_techlibs_ecp5.rst b/docs/source/cmd/index_techlibs_ecp5.rst new file mode 100644 index 000000000..29fd309cf --- /dev/null +++ b/docs/source/cmd/index_techlibs_ecp5.rst @@ -0,0 +1,5 @@ +ECP5 +------------------ + +.. autocmdgroup:: techlibs/ecp5 + :members: diff --git a/docs/source/cmd/index_techlibs_fabulous.rst b/docs/source/cmd/index_techlibs_fabulous.rst new file mode 100644 index 000000000..96f04f40a --- /dev/null +++ b/docs/source/cmd/index_techlibs_fabulous.rst @@ -0,0 +1,5 @@ +FABulous +------------------ + +.. autocmdgroup:: techlibs/fabulous + :members: diff --git a/docs/source/cmd/index_techlibs_gatemate.rst b/docs/source/cmd/index_techlibs_gatemate.rst new file mode 100644 index 000000000..951d0000b --- /dev/null +++ b/docs/source/cmd/index_techlibs_gatemate.rst @@ -0,0 +1,5 @@ +Gatemate +------------------ + +.. autocmdgroup:: techlibs/gatemate + :members: diff --git a/docs/source/cmd/index_techlibs_gowin.rst b/docs/source/cmd/index_techlibs_gowin.rst new file mode 100644 index 000000000..cdcb1c2ee --- /dev/null +++ b/docs/source/cmd/index_techlibs_gowin.rst @@ -0,0 +1,5 @@ +Gowin +------------------ + +.. autocmdgroup:: techlibs/gowin + :members: diff --git a/docs/source/cmd/index_techlibs_greenpak4.rst b/docs/source/cmd/index_techlibs_greenpak4.rst new file mode 100644 index 000000000..add1ab102 --- /dev/null +++ b/docs/source/cmd/index_techlibs_greenpak4.rst @@ -0,0 +1,5 @@ +GreenPAK4 +------------------ + +.. autocmdgroup:: techlibs/greenpak4 + :members: diff --git a/docs/source/cmd/index_techlibs_ice40.rst b/docs/source/cmd/index_techlibs_ice40.rst new file mode 100644 index 000000000..1c4b2d07a --- /dev/null +++ b/docs/source/cmd/index_techlibs_ice40.rst @@ -0,0 +1,5 @@ +iCE40 +------------------ + +.. autocmdgroup:: techlibs/ice40 + :members: diff --git a/docs/source/cmd/index_techlibs_intel.rst b/docs/source/cmd/index_techlibs_intel.rst new file mode 100644 index 000000000..6b3a26222 --- /dev/null +++ b/docs/source/cmd/index_techlibs_intel.rst @@ -0,0 +1,5 @@ +Intel (MAX10, Cyclone IV) +------------------------- + +.. autocmdgroup:: techlibs/intel + :members: diff --git a/docs/source/cmd/index_techlibs_intel_alm.rst b/docs/source/cmd/index_techlibs_intel_alm.rst new file mode 100644 index 000000000..afadfc13e --- /dev/null +++ b/docs/source/cmd/index_techlibs_intel_alm.rst @@ -0,0 +1,5 @@ +Intel ALM (Cyclone V, Arria V, Cyclone 10 GX) +--------------------------------------------- + +.. autocmdgroup:: techlibs/intel_alm + :members: diff --git a/docs/source/cmd/index_techlibs_lattice.rst b/docs/source/cmd/index_techlibs_lattice.rst new file mode 100644 index 000000000..985bf0bbd --- /dev/null +++ b/docs/source/cmd/index_techlibs_lattice.rst @@ -0,0 +1,5 @@ +Lattice +------------------ + +.. autocmdgroup:: techlibs/lattice + :members: diff --git a/docs/source/cmd/index_techlibs_lattice_nexus.rst b/docs/source/cmd/index_techlibs_lattice_nexus.rst new file mode 100644 index 000000000..d5ac4184c --- /dev/null +++ b/docs/source/cmd/index_techlibs_lattice_nexus.rst @@ -0,0 +1,5 @@ +Lattice Nexus +------------------ + +.. autocmdgroup:: techlibs/nexus + :members: diff --git a/docs/source/cmd/index_techlibs_microchip.rst b/docs/source/cmd/index_techlibs_microchip.rst new file mode 100644 index 000000000..06613a59c --- /dev/null +++ b/docs/source/cmd/index_techlibs_microchip.rst @@ -0,0 +1,5 @@ +Microchip +------------------ + +.. autocmdgroup:: techlibs/microchip + :members: diff --git a/docs/source/cmd/index_techlibs_microchip_sf2.rst b/docs/source/cmd/index_techlibs_microchip_sf2.rst new file mode 100644 index 000000000..4ebe47f33 --- /dev/null +++ b/docs/source/cmd/index_techlibs_microchip_sf2.rst @@ -0,0 +1,5 @@ +Microchip - SmartFusion2/IGLOO2 +----------------------------------- + +.. autocmdgroup:: techlibs/sf2 + :members: diff --git a/docs/source/cmd/index_techlibs_nanoxplore.rst b/docs/source/cmd/index_techlibs_nanoxplore.rst new file mode 100644 index 000000000..9eff4681c --- /dev/null +++ b/docs/source/cmd/index_techlibs_nanoxplore.rst @@ -0,0 +1,5 @@ +NanoXplore +------------------ + +.. autocmdgroup:: techlibs/nanoxplore + :members: diff --git a/docs/source/cmd/index_techlibs_quicklogic.rst b/docs/source/cmd/index_techlibs_quicklogic.rst new file mode 100644 index 000000000..54d199eb0 --- /dev/null +++ b/docs/source/cmd/index_techlibs_quicklogic.rst @@ -0,0 +1,5 @@ +QuickLogic +------------------ + +.. autocmdgroup:: techlibs/quicklogic + :members: diff --git a/docs/source/cmd/index_techlibs_xilinx.rst b/docs/source/cmd/index_techlibs_xilinx.rst new file mode 100644 index 000000000..df5112b7e --- /dev/null +++ b/docs/source/cmd/index_techlibs_xilinx.rst @@ -0,0 +1,5 @@ +Xilinx +------------------ + +.. autocmdgroup:: techlibs/xilinx + :members: diff --git a/docs/source/cmd_ref.rst b/docs/source/cmd_ref.rst index acf2d1d41..668516a0b 100644 --- a/docs/source/cmd_ref.rst +++ b/docs/source/cmd_ref.rst @@ -1,5 +1,3 @@ -.. _cmd_ref: - ================================================================================ Command line reference ================================================================================ @@ -7,10 +5,31 @@ Command line reference .. literalinclude:: /generated/yosys :start-at: Usage -.. toctree:: - :caption: Command reference - :maxdepth: 1 - :glob: +.. _cmd_ref: - /appendix/env_vars - /cmd/* +Command reference +----------------- + +.. todo:: Can we warn on command groups that aren't included anywhere? + +:ref:`List of all commands` + +.. toctree:: + :maxdepth: 2 + + /appendix/env_vars + /cmd/index_frontends + /cmd/index_backends + /cmd/index_kernel + /cmd/index_formal + +.. toctree:: + :maxdepth: 3 + + /cmd/index_passes + /cmd/index_techlibs + +.. toctree:: + :maxdepth: 2 + + /cmd/index_internal diff --git a/docs/source/code_examples/macro_commands/opt.ys b/docs/source/code_examples/macro_commands/opt.ys index cb883bc58..ebd938836 100644 --- a/docs/source/code_examples/macro_commands/opt.ys +++ b/docs/source/code_examples/macro_commands/opt.ys @@ -9,6 +9,7 @@ do opt_merge opt_share (-full only) opt_dff (except when called with -noff) + opt_hier (-hier only) opt_clean opt_expr while diff --git a/docs/source/code_examples/macro_commands/prep.ys b/docs/source/code_examples/macro_commands/prep.ys new file mode 100644 index 000000000..1bec907f6 --- /dev/null +++ b/docs/source/code_examples/macro_commands/prep.ys @@ -0,0 +1,23 @@ +#start:The following commands are executed by this synthesis command: +#end:$ +begin: + hierarchy -check [-top | -auto-top] + +coarse: + proc [-ifx] + flatten (if -flatten) + future + opt_expr -keepdc + opt_clean + check + opt -noff -keepdc + wreduce -keepdc [-memx] + memory_dff (if -rdff) + memory_memx (if -memx) + opt_clean + memory_collect + opt -noff -keepdc -fast + +check: + stat + check diff --git a/docs/source/conf.py b/docs/source/conf.py index 05dcb7d5f..ebec6915e 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -6,7 +6,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2025 YosysHQ GmbH' -yosys_ver = "0.55" +yosys_ver = "0.56" # select HTML theme html_theme = 'furo-ys' @@ -43,8 +43,12 @@ html_static_path = ['_static', "_images"] # default to no highlight highlight_language = 'none' -# default single quotes to attempt auto reference, or fallback to code +# default single quotes to attempt auto reference, or fallback to yoscrypt default_role = 'autoref' +rst_prolog = """ +.. role:: yoscrypt(code) + :language: yoscrypt +""" extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex'] @@ -64,7 +68,6 @@ if os.getenv("READTHEDOCS"): # Ensure that autosectionlabel will produce unique names autosectionlabel_prefix_document = True -autosectionlabel_maxdepth = 1 # include todos for previews extensions.append('sphinx.ext.todo') @@ -106,12 +109,14 @@ latex_elements = { # custom cmd-ref parsing/linking sys.path += [os.path.dirname(__file__) + "/../"] -extensions.append('util.cmdref') +extensions.append('util.custom_directives') # use autodocs extensions.append('sphinx.ext.autodoc') -extensions.append('util.cellref') +extensions.append('util.cell_documenter') cells_json = Path(__file__).parent / 'generated' / 'cells.json' +extensions.append('util.cmd_documenter') +cmds_json = Path(__file__).parent / 'generated' / 'cmds.json' from sphinx.application import Sphinx def setup(app: Sphinx) -> None: diff --git a/docs/source/getting_started/example_synth.rst b/docs/source/getting_started/example_synth.rst index e215586cc..ccf0d252b 100644 --- a/docs/source/getting_started/example_synth.rst +++ b/docs/source/getting_started/example_synth.rst @@ -70,7 +70,7 @@ At the bottom of the `help` output for `synth_ice40` is the complete list of commands called by this script. Let's start with the section labeled ``begin``: -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-after: begin: :end-before: flatten: @@ -143,8 +143,8 @@ line refers to the line numbers of the start/end of the corresponding ``always @`` block. In the case of an ``initial`` block, we instead see the ``PROC`` referring to line 0. -To handle these, let us now introduce the next command: :doc:`/cmd/proc`. `proc` -is a macro command like `synth_ice40`. Rather than modifying the design +To handle these, let us now introduce the next command: :cmd:title:`proc`. +`proc` is a macro command like `synth_ice40`. Rather than modifying the design directly, it instead calls a series of other commands. In the case of `proc`, these sub-commands work to convert the behavioral logic of processes into multiplexers and registers. Let's see what happens when we run it. For now, we @@ -188,7 +188,7 @@ opt_expr `. .. note:: - :doc:`/cmd/clean` can also be called with two semicolons after any command, + :cmd:title:`clean` can also be called with two semicolons after any command, for example we could have called :yoscrypt:`opt_expr;;` instead of :yoscrypt:`opt_expr; clean`. You may notice some scripts will end each line with ``;;``. It is beneficial to run `clean` before inspecting intermediate @@ -215,8 +215,8 @@ Note that if we tried to run this command now then we would get an error. This is because we already removed all of the modules other than ``addr_gen``. We could restart our shell session, but instead let's use two new commands: -- :doc:`/cmd/design`, and -- :doc:`/cmd/read_verilog`. +- :cmd:title:`design`, and +- :cmd:title:`read_verilog`. .. literalinclude:: /code_examples/fifo/fifo.out :language: doscon @@ -251,7 +251,7 @@ our design won't run into this issue, we can skip the ``-defer``. We can also run `proc` now to finish off the full :ref:`synth_begin`. Because the design schematic is quite large, we will be showing just the data path for the ``rdata`` output. If you would like to see the entire design for yourself, -you can do so with :doc:`/cmd/show`. Note that the `show` command only works +you can do so with :cmd:title:`show`. Note that the `show` command only works with a single module, so you may need to call it with :yoscrypt:`show fifo`. :ref:`show_intro` section in :doc:`/getting_started/scripting_intro` has more on how to use `show`. @@ -283,7 +283,7 @@ Flattening At this stage of a synthesis flow there are a few other commands we could run. In `synth_ice40` we get these: -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-after: flatten: :end-before: coarse: @@ -355,7 +355,7 @@ Part 1 In the iCE40 flow, we start with the following commands: -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-after: coarse: :end-before: wreduce @@ -371,7 +371,7 @@ wasting time on something we know is impossible. Next up is :yoscrypt:`opt -nodffe -nosdff` performing a set of simple optimizations on the design. This command also ensures that only a specific subset of FF types are included, in preparation for the next command: -:doc:`/cmd/fsm`. Both `opt` and `fsm` are macro commands which are explored in +:cmd:title:`fsm`. Both `opt` and `fsm` are macro commands which are explored in more detail in :doc:`/using_yosys/synthesis/opt` and :doc:`/using_yosys/synthesis/fsm` respectively. @@ -403,7 +403,7 @@ Part 2 The next group of commands performs a series of optimizations: -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-at: wreduce :end-before: t:$mul @@ -411,7 +411,7 @@ The next group of commands performs a series of optimizations: :caption: ``coarse`` section (part 2) :name: synth_coarse2 -First up is :doc:`/cmd/wreduce`. If we run this we get the following: +First up is :cmd:title:`wreduce`. If we run this we get the following: .. literalinclude:: /code_examples/fifo/fifo.out :language: doscon @@ -432,7 +432,7 @@ the schematic and see the output of that cell has now changed. ``rdata`` output after `wreduce` -The next two (new) commands are :doc:`/cmd/peepopt` and :doc:`/cmd/share`. +The next two (new) commands are :cmd:title:`peepopt` and :cmd:title:`share`. Neither of these affect our design, and they're explored in more detail in :doc:`/using_yosys/synthesis/opt`, so let's skip over them. :yoscrypt:`techmap -map +/cmp2lut.v -D LUT_WIDTH=4` optimizes certain comparison operators by @@ -440,7 +440,7 @@ converting them to LUTs instead. The usage of `techmap` is explored more in :doc:`/using_yosys/synthesis/techmap_synth`. Our next command to run is -:doc:`/cmd/memory_dff`. +:cmd:title:`memory_dff`. .. literalinclude:: /code_examples/fifo/fifo.out :language: doscon @@ -475,7 +475,7 @@ will only be performed if called with the ``-dsp`` flag: :yoscrypt:`synth_ice40 -dsp`. While our example has nothing that could be mapped to DSPs we can still take a quick look at the commands here and describe what they do. -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-at: t:$mul :end-before: alumacc @@ -514,7 +514,7 @@ Part 4 That brings us to the fourth and final part for the iCE40 synthesis flow: -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-at: alumacc :end-before: map_ram: @@ -543,7 +543,7 @@ Once these cells have been inserted, the call to `opt` can combine cells which are now identical but may have been missed due to e.g. the difference between `$add` and `$sub`. -The other new command in this part is :doc:`/cmd/memory`. `memory` is another +The other new command in this part is :cmd:title:`memory`. `memory` is another macro command which we examine in more detail in :doc:`/using_yosys/synthesis/memory`. For this document, let us focus just on the step most relevant to our example: `memory_collect`. Up until this point, @@ -594,7 +594,7 @@ Memory blocks Mapping to hard memory blocks uses a combination of `memory_libmap` and `techmap`. -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-after: map_ram: :end-before: map_ffram: @@ -636,7 +636,7 @@ into flip flops (the ``logic fallback``) with `memory_map`. .. |techlibs/ice40/brams_map.v| replace:: :file:`techlibs/ice40/brams_map.v` .. _techlibs/ice40/brams_map.v: https://github.com/YosysHQ/yosys/tree/main/techlibs/ice40/brams_map.v -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-after: map_ffram: :end-before: map_gates: @@ -671,7 +671,7 @@ an explosion in cells as multi-bit `$mux` and `$adffe` are replaced with single-bit `$_MUX_` and `$_DFFE_PP0P_` cells, while the `$alu` is replaced with primitive `$_OR_` and `$_NOT_` gates and a `$lut` cell. -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-after: map_gates: :end-before: map_ffs: @@ -700,7 +700,7 @@ mapped to hardware into gate-level primitives. This includes optimizing `$_MUX_` cells where one of the inputs is a constant ``1'0``, replacing it instead with an `$_AND_` cell. -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-after: map_ffs: :end-before: map_luts: @@ -725,7 +725,7 @@ LUTs `abc`. For more on what these do, and what the difference between these two commands are, refer to :doc:`/using_yosys/synthesis/abc`. -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-after: map_luts: :end-before: map_cells: @@ -742,7 +742,7 @@ commands are, refer to :doc:`/using_yosys/synthesis/abc`. Finally we use `techmap` to map the generic `$lut` cells to iCE40 ``SB_LUT4`` cells. -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-after: map_cells: :end-before: check: @@ -784,19 +784,18 @@ Final steps The next section of the iCE40 synth flow performs some sanity checking and final tidy up: -.. literalinclude:: /cmd/synth_ice40.rst +.. literalinclude:: /code_examples/macro_commands/synth_ice40.ys :language: yoscrypt :start-after: check: - :end-before: blif: :dedent: :name: check :caption: ``check`` section The new commands here are: -- :doc:`/cmd/autoname`, -- :doc:`/cmd/stat`, and -- :doc:`/cmd/blackbox`. +- :cmd:title:`autoname`, +- :cmd:title:`stat`, and +- :cmd:title:`blackbox`. The output from `stat` is useful for checking resource utilization; providing a list of cells used in the design and the number of each, as well as the number @@ -835,9 +834,9 @@ Synthesis output The iCE40 synthesis flow has the following output modes available: -- :doc:`/cmd/write_blif`, -- :doc:`/cmd/write_edif`, and -- :doc:`/cmd/write_json`. +- `write_blif`, +- `write_edif`, and +- `write_json`. As an example, if we called :yoscrypt:`synth_ice40 -top fifo -json fifo.json`, our synthesized ``fifo`` design will be output as :file:`fifo.json`. We can @@ -848,4 +847,4 @@ is beyond the scope of this documentation. .. _nextpnr: https://github.com/YosysHQ/nextpnr -.. seealso:: :doc:`/cmd/synth_ice40` +.. seealso:: :cmd:title:`synth_ice40` diff --git a/docs/source/getting_started/scripting_intro.rst b/docs/source/getting_started/scripting_intro.rst index 01954c661..c44ce82a8 100644 --- a/docs/source/getting_started/scripting_intro.rst +++ b/docs/source/getting_started/scripting_intro.rst @@ -26,7 +26,7 @@ of the comment is a semicolon ``;`` or a new line. .. code-block:: :caption: Using the ``-p`` option - $ yosys -p "read_verilog fifo.v; :this is a comment; prep" + $ yosys -p 'read_verilog fifo.v; :this is a comment; prep' .. warning:: @@ -42,6 +42,13 @@ will be raised by Yosys. `exec` provides a much more flexible way of executing commands, allowing the output to be logged and more control over when to generate errors. +.. warning:: + + Take care when using the ``yosys -p`` option. Some shells such as bash will + perform substitution options inside of a double quoted string, such as ``!`` + for history substitution and ``$`` for variable substitution; single quotes + should be used instead to pass the string to Yosys without substitution. + The synthesis starter script ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -122,7 +129,7 @@ module. Detailed documentation of the select framework can be found under :doc:`/using_yosys/more_scripting/selections` or in the command reference at -:doc:`/cmd/select`. +:cmd:title:`select`. .. _show_intro: @@ -219,7 +226,7 @@ those used in options, must be a single expression instead. .. _GraphViz color docs: https://graphviz.org/doc/info/colors For all of the options available to `show`, check the command reference at -:doc:`/cmd/show`. +:cmd:title:`show`. .. seealso:: :ref:`interactive_show` on the :doc:`/using_yosys/more_scripting/interactive_investigation` page. diff --git a/docs/source/index.rst b/docs/source/index.rst index 61dc114ef..403100093 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -5,7 +5,7 @@ Yosys Open SYnthesis Suite Yosys is an open source framework for RTL synthesis. To learn more about Yosys, see :doc:`/introduction`. For a quick guide on how to get started using Yosys, check out :doc:`/getting_started/index`. For the complete list of commands -available, go to :ref:`commandindex`. +available, go to :ref:`cmd_ref`. .. todo:: look into command ref improvements diff --git a/docs/source/using_yosys/bugpoint.rst b/docs/source/using_yosys/bugpoint.rst new file mode 100644 index 000000000..c524470af --- /dev/null +++ b/docs/source/using_yosys/bugpoint.rst @@ -0,0 +1,446 @@ +Minimizing failing (or bugged) designs +====================================== + +.. TODO:: pending merge of https://github.com/YosysHQ/yosys/pull/5068 + +This document is a how-to guide for reducing problematic designs to the bare +minimum needed for reproducing the issue. This is a Yosys specific alternative +to the Stack Overflow article: `How to create a Minimal, Reproducible Example`_, +and is intended to help when there's something wrong with your design, or with +Yosys itself. + +.. _How to create a Minimal, Reproducible Example: https://stackoverflow.com/help/minimal-reproducible-example + +.. note:: + + This guide assumes a moderate degree of familiarity with Yosys and requires + some amount of problem solving ability. + + +Before you start +---------------- + +The first (and often overlooked) step, is to check for and *read* any error +messages or warnings. Passing the ``-q`` flag when running Yosys will make it +so that only warnings and error messages are written to the console. Don't just +read the last message either, there may be warnings that indicate a problem +before it happens. While some things may only be regarded as warnings, such as +multiple drivers for the same signal or logic loops, these can cause problems in +some synthesis flows but not others. + +A Yosys error (one that starts with ``ERROR:``) may give you a line number from +your design, or the name of the object causing issues. If so, you may already +have enough information to resolve the problem, or at least understand why it's +happening. + +.. note:: + + If you're not already, try using the latest version from the `Yosys GitHub`_. + You may find that your issue has already been fixed! And even if it isn't, + testing with two different versions is a good way to ensure reproducibility. + +.. _Yosys GitHub: https://github.com/YosysHQ/yosys + +Another thing to be aware of is that Yosys generally doesn't perform rigorous +checking of input designs to ensure they are valid. This is especially true for +the `read_verilog` frontend. It is instead recommended that you try load it +with `iverilog`_ or `verilator`_ first, as an invalid design can often lead to +unexpected issues. + +.. _iverilog: https://steveicarus.github.io/iverilog/ +.. _verilator: https://www.veripool.org/verilator/ + +If you're using a custom synthesis script, try take a bit of time to figure out +which command is failing. Calling ``echo on`` at the start of your script will +`echo` each command executed; the last echo before the error should then be +where the error has come from. Check the help message for the failing command; +does it indicate limited support, or mention some other command that needs to be +run first? You can also try to call `check` and/or ``hierarchy -check`` before +the failure to see if they report and errors or warnings. + + +Minimizing RTLIL designs with bugpoint +-------------------------------------- + +Yosys provides the `bugpoint` command for reducing a failing design to the +smallest portion of that design which still results in failure. While initially +developed for Yosys crashes, `bugpoint` can also be used for designs that lead +to non-fatal errors, or even failures in other tools that use the output of a +Yosys script. + +.. note:: + + Make sure to back up your code (design source and yosys script(s)) before + making any modifications. Even if the code itself isn't important, this can + help avoid "losing" the error while trying to debug it. + +Can I use bugpoint? +~~~~~~~~~~~~~~~~~~~ + +The first thing to be aware of is that `bugpoint` is not available in every +build of Yosys. Because the command works by invoking external processes, it +requires that Yosys can spawn executables. Notably this means `bugpoint` is not +able to be used in WebAssembly builds such as that available via YoWASP. The +easiest way to check your build of Yosys is by running ``yosys -h bugpoint``. If +Yosys displays the help text for `bugpoint` then it is available for use. + +.. code-block:: console + :caption: `bugpoint` is unavailable + + $ yosys -h bugpoint + + -- Running command `help bugpoint' -- + No such command or cell type: bugpoint + +Next you need to separate loading the design from the failure point; you should +be aiming to reproduce the failure by running ``yosys -s -s +``. If the failure occurs while loading the design, such as during +`read_verilog` you will instead have to minimize the input design yourself. +Check out the instructions for :ref:`using_yosys/bugpoint:minimizing verilog +designs` below. + +.. note:: + + You should also be able to run the two scripts separately, calling first + ``yosys -s -p 'write_rtlil design.il'`` and then ``yosys -s + design.il``. If this doesn't work then it may mean that the + failure isn't reproducible from RTLIL and `bugpoint` won't work either. + +When we talk about failure points here, it doesn't just mean crashes or errors +in Yosys. The ```` script can also be a user-defined failure such +as the `select` command with one of the ``-assert-*`` options; an example where +this might be useful is when a pass is supposed to remove a certain kind of +cell, but there is some edge case where the cell is not removed. Another +use-case would be minimizing a design which fails with the `equiv_opt` command, +suggesting that the optimization in question alters the circuit in some way. + +It is even possible to use `bugpoint` with failures *external* to Yosys, by +making use of the `exec` command in ````. This is especially useful +when Yosys is outputting an invalid design, or when some other tool is +incompatible with the design. Be sure to use the ``exec -expect-*`` options so +that the pass/fail can be detected correctly. Multiple calls to `exec` can be +made, or even entire shell scripts: + +.. code-block:: yoscrypt + + exec -expect-return 1 --bash + +Our final failure we can use with `bugpoint` is one returned by a wrapper +process, such as ``valgrind`` or ``timeout``. In this case you will be calling +something like `` yosys -s design.il``. Here, Yosys is +run under a wrapper process which checks for some failure state, like a memory +leak or excessive runtime. + + +How do I use bugpoint? +~~~~~~~~~~~~~~~~~~~~~~ + +At this point you should have: + +1. either an RTLIL file containing the design to minimize (referred to here as + ``design.il``), or a Yosys script, ````, which loads it; and +2. a Yosys script, ````, which produces the failure and returns a + non-zero return status. + +Now call ``yosys -qq -s design.il`` and take note of the error(s) +that get printed. A template script, ````, is provided here which +you can use. Make sure to configure it with the correct filenames and use only +one of the methods to load the design. Fill in the ``-grep`` option with the +error message printed just before. If you are using a wrapper process for your +failure state, add the ``-runner ""`` option to the `bugpoint` call. + +.. code-block:: yoscrypt + :caption: ```` template script + + # Load design + read_rtlil design.il + ## OR + script + + # Call bugpoint with failure + bugpoint -script -grep "" + + # Save minimized design + write_rtlil min.il + +The ``-grep`` option is used to search the log file generated by the Yosys under +test. If the error message is generated by something else, such as a wrapper +process or compiler sanitizer, then you should instead use ``-err_grep``. For +an OS error, like a SEGFAULT, you can also use ``-expect-return`` to check the +error code returned. + +.. note:: + + Checking the error message or return status is optional, but highly + recommended. `bugpoint` can quite easily introduce bugs by creating + malformed designs that commands were not intended to handle. By having some + way to check the error, `bugpoint` can ensure that it is the *right* error + being reproduced. This is even more important when ```` contains + more than one command. + +By default, `bugpoint` is able to remove any part of the design. In order to +keep certain parts, for instance because you already know they are related to +the failure, you can use the ``bugpoint_keep`` attribute. This can be done with +``(* bugpoint_keep *)`` in Verilog, ``attribute \bugpoint_keep 1`` in RTLIL, or +``setattr -set bugpoint_keep 1 [selection]`` from a Yosys script. It is also +possible to limit `bugpoint` to only removing certain *kinds* of objects, such +as only removing entire modules or cells (instances of modules). For more about +the options available, check ``help bugpoint`` or :cmd:title:`bugpoint`. + +In some situations, it may also be helpful to use `setenv` before `bugpoint` to +set environment variables for the spawned processes. An example of this is +``setenv UBSAN_OPTIONS halt_on_error=1`` for where you are trying to raise an +error on undefined behaviour but only want the child process to halt on error. + +.. note:: + + Using `setenv` in this way may or may not affect the current process. For + instance the ``UBSAN_OPTIONS halt_on_error`` here only affects child + processes, as does the :doc:`Yosys environment variable` + ``ABC`` because they are only read on start-up. While others, such as + ``YOSYS_NOVERIFIC`` and ``HOME``, are evaluated each time they are used. + +Once you have finished configuration, you can now run ``yosys ``. +The first thing `bugpoint` will do is test the input design fails. If it +doesn't, make sure you are using the right ``yosys`` executable; unless the +``-yosys`` option is provided, it will use whatever the shell defaults to, *not* +the current ``yosys``. If you are using the ``-runner`` option, try replacing +the `bugpoint` command with ``write_rtlil test.il`` and then on a new line, +``! yosys -s test.il`` to check it works as expected and +returns a non-zero status. + +.. seealso:: + + For more on script parsing and the use of ``!``, check out + :ref:`getting_started/scripting_intro:script parsing`. + +Depending on the size of your design, and the length of your ````, +`bugpoint` may take some time; remember, it will run ``yosys -s `` +on each iteration of the design. The bigger the design, the more iterations. +The longer the ````, the longer each iteration will take. As the +design shrinks and `bugpoint` converges, each iteration should take less and +less time. Once all simplifications are exhausted and there are no more objects +that can be removed, the script will continue and the minimized design can be +saved. + + +What do I do with the minimized design? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +First off, check the minimized design still fails. This is especially important +if you're not using `write_rtlil` to output the minimized design. For example, +if you ran :ref:`bugpoint_script` below, then calling ``yosys -s +min.v`` should still fail in the same way. + +.. code-block:: yoscrypt + :caption: example `bugpoint` minimizer + :name: bugpoint_script + + read_verilog design.v + bugpoint -script + write_verilog min.v + +The `write_rtlil` command is generally more reliable, since `bugpoint` will have +run that exact code through the failing script. Other ``write_*`` commands +convert from the RTLIL and then back again during the ``read_*`` which can +result in differences which mean the design no longer fails. + +.. note:: + + Simply calling Yosys with the output of ``write_*``, as in ``yosys -s + min.v``, does not guarantee that the corresponding ``read_*`` + will be used. For more about this, refer to + :doc:`/using_yosys/more_scripting/load_design`, or load the design explicitly + with ``yosys -p 'read_verilog min.v' -s ``. + +Once you've verified the failure still happens, check out +:ref:`using_yosys/bugpoint:identifying issues` for more on what to do next. + + +Minimizing Verilog designs +-------------------------- + +.. seealso:: + + This section is not specific to Yosys, so feel free to use another guide such + as Stack Overflow's `How to create a Minimal, Reproducible Example`_. + +Be sure to check any errors or warnings for messages that might identify source +lines or object names that might be causing the failure, and back up your source +code before modifying it. If you have multiple source files, you should start +by reducing them down to a single file. If a specific file is failing to read, +try removing everything else and just focus on that one. If your source uses +the ``include`` directive, replace it with the contents of the file referenced. + +Unlike RTLIL designs where we can use `bugpoint`, Yosys does not provide any +tools for minimizing Verilog designs. Instead, you should use an external tool +like `C-Reduce`_ (with the ``--not-c`` flag) or `sv-bugpoint`_. + +.. _C-Reduce: https://github.com/csmith-project/creduce +.. _sv-bugpoint: https://github.com/antmicro/sv-bugpoint + +C-Reduce +~~~~~~~~ + +As a very brief overview for using C-Reduce, you want your failing source design +(``test.v``), and some shell script which checks for the error being +investigated (``test.sh``). Below is an :ref:`egtest` which uses `logger` and +the ``-expect error "" 1`` option to perform a similar role to +``bugpoint -grep``, along with ``verilator`` to lint the code and make sure it +is still valid. + +.. code-block:: bash + :caption: Example test.sh for C-Reduce + :name: egtest + + #!/bin/bash + verilator --lint-only test.v &&/ + yosys -p 'logger -expect error "unsupported" 1; read_verilog test.v' + +.. code-block:: verilog + :caption: input test.v + + module top(input clk, a, b, c, output x, y, z); + always @(posedge clk) begin + if (a == 1'b1) + $stop; + end + assign x = a; + assign y = a ^ b; + assign z = c; + endmodule + +In this example ``read_verilog test.v`` is giving an error message that contains +the string "unsupported" because the ``$stop`` system task is only supported in +``initial`` blocks. By calling ``creduce ./test.sh test.v --not-c`` we can +minimize the design to just the failing code, while still being valid Verilog. + +.. code-block:: verilog + :caption: output test.v + + module a; + always begin $stop; + end endmodule + + +sv-bugpoint +~~~~~~~~~~~ + +sv-bugpoint works quite similarly to C-Reduce, except it requires an output +directory to be provided and the check script needs to accept the target file as +an input argument: ``sv-bugpoint outDir/ test.sh test.v`` + +.. code-block:: bash + :caption: Example test.sh for sv-bugpoint + + #!/bin/bash + verilator --lint-only $1 &&/ + yosys -p "logger -expect error \"unsupported\" 1; read_verilog $1" + +Notice that the commands for ``yosys -p`` are now in double quotes (``"``), and +the quotes around the error string are escaped (``\"``). This is necessary for +the ``$1`` argument subsitution to work correctly. + + +Doing it manually +~~~~~~~~~~~~~~~~~ + +If for some reason you are unable to use a tool to minimize your code, you can +still do it manually. But it can be a time consuming process and requires a lot +of iteration. At any point in the process, you can check for anything that is +unused or totally disconnected (ports, wires, etc) and remove them. If a +specific module is causing the problem, try to set that as the top module +instead. Any parameters should have their default values changed to match the +failing usage. + +As a rule of thumb, try to split things roughly in half at each step; similar to +a "binary search". If you have 10 cells (instances of modules) in your top +module, and have no idea what is causing the issue, split them into two groups +of 5 cells. For each group of cells, try remove them and see if the failure +still happens. If the error still occurs with the first group removed, but +disappears when the second group is removed, then the first group can be safely +removed. If a module has no more instances, remove it entirely. Repeat this +for each remaining group of cells until each group only has 1 cell in it and no +more cells can be removed without making the error disappear. You can also +repeat this for each module still in your design. + +After minimizing the number of cells, do the same for the process blocks in your +top module. And again for any generate blocks and combinational blocks. +Remember to check for any ports or signals which are no longer used and remove +those too. Any signals which are written but never read can also be removed. + +.. note:: + + Depending on where the design is failing, there are some commands which may + help in identifying unused objects in the design. `hierarchy` will identify + which modules are used and which are not, but check for ``$paramod`` modules + before removing unused ones. ``debug clean`` will list all unused wires in + each module, as well as unused cells which were automatically generated + (giving the line number of the source that generated them). Adding the + ``-purge`` flag will also include named wires that would normally be ignored + by `clean`. Though when there are large numbers of unused wires it is often + easier to just delete sections of the code and see what happens. + +Next, try to remove or reduce assignments (``a = b``) and operations (``a + +b``). A good place to start is by checking for any wires/registers which are +read but never written. Try removing the signal declaration and replacing +references to it with ``'0`` or ``'x``. Do this with any constants too. Try to +replace strings with numeric values, and wide signals with smaller ones, then +see if the error persists. + +Check if there are any operations that you can simplify, like replacing ``a & +'0`` with ``'0``. If you have enable or reset logic, try removing it and see if +the error still occurs. Try reducing ``if .. else`` and ``case`` blocks to a +single case. Even if that doesn't work, you may still be able to remove some +paths; start with cases that appear to be unreachable and go from there. + +.. note:: + + When sharing code on the `Yosys GitHub`_, please try to keep things in + English. Declarations and strings should stick to the letters a-z and + numbers 0-9, unless the error is arising because of the names/characters + used. + + +Identifying issues +------------------ + +When identifying issues, it is quite useful to understand the conditions under +which the issue is occurring. While there are occasionally bugs that affect a +significant number of designs, Yosys changes are tested on a variety of designs +and operating systems which typically catch any such issues before they make it +into the main branch. So what is is it about your situation that makes it +unusual? + +.. note:: + + If you have access to a different platform you could also check if your issue + is reproducible there. Some issues may be specific to the platform or build + of Yosys. + +Try to match the minimized design back to its original context. Could you +achieve the same thing a different way, and if so, does this other method have +the same issue? Try to change the design in small ways and see what happens; +while `bugpoint` can reduce and simplify a design, it doesn't *change* much. +What happens if you change operators, for example a left shift (or `$shl`) to a +right shift (or `$shr`)? Try to see if the issue is tied to specific +parameters, widths, or values. + +Search `the existing issues`_ and see if someone has already made a bug report. +This is where changing the design and finding the limits of what causes the +failure really comes in handy. If you're more familiar with how the problem can +arise, you may be able to find a related issue more easily. If an issue already +exists for one case of the problem but you've found other cases, you can comment +on the issue and help get it solved. If there are no existing or related issues +already, then check out the steps for +:ref:`yosys_internals/extending_yosys/contributing:reporting bugs`. + +.. _the existing issues: https://github.com/YosysHQ/yosys/issues + +.. warning:: + + If you are using a fuzzer to find bugs, follow the instructions for + :doc:`/yosys_internals/extending_yosys/advanced_bugpoint`. **Do not** open + more than one fuzzer generated issue at a time if you can not identify the + root cause. If you are found to be doing this, your issues may be closed + without further investigation. diff --git a/docs/source/using_yosys/index.rst b/docs/source/using_yosys/index.rst index 55bd5c291..b243d431e 100644 --- a/docs/source/using_yosys/index.rst +++ b/docs/source/using_yosys/index.rst @@ -15,3 +15,5 @@ ways Yosys can interact with designs for a deeper investigation. synthesis/index more_scripting/index + bugpoint + verilog diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst index e9c9bc9ac..0d1a17503 100644 --- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst +++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst @@ -311,8 +311,8 @@ cells, as the net-names are usually suppressed in the circuit diagram if they are auto-generated. Note that the output is in the RTLIL representation, described in :doc:`/yosys_internals/formats/rtlil_rep`. -Interactive Design Investigation -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Design Investigation +~~~~~~~~~~~~~~~~~~~~ Yosys can also be used to investigate designs (or netlists created from other tools). @@ -323,10 +323,10 @@ tools). design into an equivalent design that is easier to analyse. - Commands such as `eval` and `sat` can be used to investigate the behavior of the circuit. -- :doc:`/cmd/show`. -- :doc:`/cmd/dump`. -- :doc:`/cmd/add` and :doc:`/cmd/delete` can be used to modify and reorganize a - design dynamically. +- :cmd:title:`show`. +- :cmd:title:`dump`. +- :cmd:title:`add` and :cmd:title:`delete` can be used to modify and reorganize + a design dynamically. The code used is included in the Yosys code base under |code_examples/scrambler|_. @@ -358,7 +358,7 @@ reorganizing a module in Yosys and checking the resulting circuit. .. figure:: /_images/code_examples/scrambler/scrambler_p02.* :class: width-helper invert-helper -Analyzing the resulting circuit with :doc:`/cmd/eval`: +Analyzing the resulting circuit with :cmd:title:`eval`: .. todo:: replace inline code diff --git a/docs/source/using_yosys/more_scripting/load_design.rst b/docs/source/using_yosys/more_scripting/load_design.rst index bbc55a36b..9aa028418 100644 --- a/docs/source/using_yosys/more_scripting/load_design.rst +++ b/docs/source/using_yosys/more_scripting/load_design.rst @@ -1,11 +1,107 @@ Loading a design -~~~~~~~~~~~~~~~~ +---------------- -keyword: Frontends +.. _input files: -- :doc:`/cmd/read_verilog` +Input files on the command line +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. todo:: include ``read_verilog < ``read -vlog2k`` + + ``.sv`` -> ``read -sv`` + + ``.vhd`` and ``.vhdl`` -> ``read -vhdl`` + + ``.blif`` and ``.eblif`` -> `read_blif` + + ``.json`` -> `read_json` + + ``.il`` -> `read_rtlil` (direct textual representation of Yosys internal + state) + +- command line also supports + + + ``.ys`` -> `script` + + ``.tcl`` -> `tcl` + + ``-`` -> reads stdin and treats it as a script + +The `read` command +~~~~~~~~~~~~~~~~~~ + +- standard method of loading designs +- also for defining macros and include directories +- uses `verific` command if available + + + ``-verific`` and ``-noverific`` options to enforce with/without Verific + + check ``help read`` for more about the options available and the filetypes + supported + + elaborate designs with ``verific -import [options] `` (or use + `hierarchy`) + +- fallback to `read_verilog` with ``-defer`` option + + + does not compile design until `hierarchy` command as discussed in + :doc:`/getting_started/example_synth` + + more similar to `verific` behaviour + +- ``read -define`` et al mapped to `verific` or `verilog_defines` +- similarly, ``read -incdir`` et al mapped to `verific` or `verilog_defaults` + +.. note:: + + The Verific frontend for Yosys, which provides the :cmd:ref:`verific` + command, requires Yosys to be built with Verific. For full functionality, + custom modifications to the Verific source code from YosysHQ are required, + but limited useability can be achieved with some stock Verific builds. Check + :doc:`/yosys_internals/extending_yosys/build_verific` for more. + +.. _Frontend: + +Yosys frontends +~~~~~~~~~~~~~~~ + +- :doc:`/cmd/index_frontends` +- typically start with ``read_`` +- built-in support for heredocs + + + in-line code with ``< hierarchy -check``. + +.. note:: + + It may also be helpful to use the `log` command to add messages which you can + then search for either in the terminal or the logfile. This can be quite + useful if your script contains script-passes, like the + :doc:`/using_yosys/synthesis/synth`, which call many sub-commands and you're + not sure exactly which script-pass is calling the failing command. + + +Minimizing scripts +------------------ + +.. warning:: + + This section is intended as **advanced usage**, and generally not necessary + for normal bug reports. + +If you're using a command line prompt, such as ``yosys -p 'synth_xilinx' -o +design.json design.v``, consider converting it to a script. It's generally much +easier to iterate over changes to a script in a file rather than one on the +command line, as well as being better for sharing with others. + +.. code-block:: yoscrypt + :caption: example script, ``script.ys``, for prompt ``yosys -p 'synth_xilinx' -o design.json design.v`` + + read_verilog design.v + synth_xilinx + write_json design.json + +Next up you want to remove everything *after* the error occurs. If your final +command calls sub-commands, replace it with its contents first. In the case of +the :doc:`/using_yosys/synthesis/synth`, as well as certain other script-passes, +you can use the ``-run`` option to simplify this. For example we can replace +``synth -top -lut`` with the :ref:`replace_synth`. The options ``-top + -lut`` can be provided to each `synth` step, or to just the step(s) where +it is relevant, as done here. + +.. code-block:: yoscrypt + :caption: example replacement script for `synth` command + :name: replace_synth + + synth -top -run :coarse + synth -lut -run coarse:fine + synth -lut -run fine:check + synth -run check: + +Say we ran :ref:`replace_synth` and were able to remove the ``synth -run +check:`` and still got our error, then we check the log and we see the last +thing before the error was ``7.2. Executing MEMORY_MAP pass (converting memories +to logic and flip-flops)``. By checking the output of ``yosys -h synth`` (or the +`synth` help page) we can see that the `memory_map` pass is called in the +``fine`` step. We can then update our script to the following: + +.. code-block:: yoscrypt + :caption: example replacement script for `synth` when `memory_map` is failing + + synth -top -run :fine + opt -fast -full + memory_map + +By giving `synth` the option ``-run :fine``, we are telling it to run from the +beginning of the script until the ``fine`` step, where we then give it the exact +commands to run. There are some cases where the commands given in the help +output are not an exact match for what is being run, but are instead a +simplification. If you find that replacing the script-pass with its contents +causes the error to disappear, or change, try calling the script-pass with +``echo on`` to see exactly what commands are being called and what options are +used. + +.. warning:: + + Before continuing further, *back up your code*. The following steps can + remove context and lead to over-minimizing scripts, hiding underlying issues. + Check out :ref:`yosys_internals/extending_yosys/advanced_bugpoint:Why + context matters` to learn more. + +When a problem is occurring many steps into a script, minimizing the design at +the start of the script isn't always enough to identify the cause of the issue. +Each extra step of the script can lead to larger sections of the input design +being needed for the specific problem to be preserved until it causes a crash. +So to find the smallest possible reproducer it can sometimes be helpful to +remove commands prior to the failure point. + +The simplest way to do this is by writing out the design, resetting the current +state, and reading back the design: + +.. code-block:: yoscrypt + + write_rtlil ; design -reset; read_rtlil ; + +In most cases, this can be inserted immediately before the failing command while +still producing the error, allowing you to :ref:`minimize your +RTLIL` with the +```` output. For our previous example with `memory_map`, if +:ref:`map_reset` still gives the same error, then we should now be able to call +``yosys design.il -p 'memory_map'`` to reproduce it. + +.. code-block:: yoscrypt + :caption: resetting the design immediately before failure + :name: map_reset + + synth -top -run :fine + opt -fast -full + write_rtlil design.il; design -reset; read_rtlil design.il; + memory_map + +If that doesn't give the error (or doesn't give the same error), then you should +try to move the write/reset/read earlier in the script until it does. If you +have no idea where exactly you should put the reset, the best way is to use a +"binary search" type approach, reducing the possible options by half after each +attempt. + +.. note:: + + By default, `write_rtlil` doesn't include platform specific IP blocks and + other primitive cell models which are typically loaded with a ``read_verilog + -lib`` command at the start of the synthesis script. You may have to + duplicate these commands *after* the call to ``design -reset``. It is also + possible to write out *everything* with ``select =*; write_rtlil -selected + ``. + +As an example, your script has 16 commands in it before failing on the 17th. If +resetting immediately before the 17th doesn't reproduce the error, try between +the 8th and 9th (8 is half of the total 16). If that produces the error then +you can remove everything before the `read_rtlil` and try reset again in the +middle of what's left, making sure to use a different name for the output file +so that you don't overwrite what you've already got. If the error isn't +produced then you need to go earlier still, so in this case you would do between +the 4th and 5th (4 is half of the previous 8). Repeat this until you can't +reduce the remaining commands any further. + +A more conservative, but more involved, method is to remove or comment out +commands prior to the failing command. Each command, or group of commands, can +be disabled one at a time while checking if the error still occurs, eventually +giving the smallest subset of commands needed to take the original input through +to the error. The difficulty with this method is that depending on your design, +some commands may be necessary even if they aren't needed to reproduce the +error. For example, if your design includes ``process`` blocks, many commands +will fail unless you run the `proc` command. While this approach can do a +better job of maintaining context, it is often easier to *recover* the context +after the design has been minimized for producing the error. For more on +recovering context, checkout +:ref:`yosys_internals/extending_yosys/advanced_bugpoint:Why context matters`. + + +Why context matters +------------------- + +Sometimes when a command is raising an error, you're seeing a symptom rather +than the underlying issue. It's possible that an earlier command may be putting +the design in an invalid state, which isn't picked up until the error is raised. +This is particularly true for the pre-packaged +:doc:`/using_yosys/synthesis/synth`, which rely on a combination of generic and +architecture specific passes. As new features are added to Yosys and more +designs are supported, the types of cells output by a pass can grow and change; +and sometimes this leads to a mismatch in what a pass is intended to handle. + +If you minimized your script, and removed commands prior to the failure to get a +smaller reproducer, try to work backwards and find which commands may have +contributed to the design failing. From the minimized design you should have +some understanding of the cell or cells which are producing the error; but where +did those cells come from? The name and/or type of the cell can often point you +in the right direction: + +.. code-block:: + + # internal cell types start with a $ + # lowercase for word-level, uppercase for bit-level + $and + $_AND_ + + # cell types with $__ are typically intermediate cells used in techmapping + $__MUL16X16 + + # cell types without a $ are either user-defined or architecture specific + my_module + SB_MAC16 + + # object names might give you the name of the pass that created them + $procdff$1204 + $memory\rom$rdmux[0][0][0]$a$1550 + + # or even the line number in the Yosys source + $auto$muxcover.cc:557:implement_best_cover$2152 + $auto$alumacc.cc:495:replace_alu$1209 + +Try running the unminimized script and search the log for the names of the +objects in your minimized design. In the case of cells you can also search for +the type of the cell. Remember that calling `stat` will list all the types of +cells currently used in the design, and ``select -list =*`` will list the names +of of all the current objects. You can add these commands to your script, or +use an interactive terminal to run each command individually. Adding them to +the script can be more repeatable, but if it takes a long time to run to the +point you're interested in then an interactive shell session can give you more +flexibility once you reach that point. You can also add a call to the `shell` +command at any point in a script to start an interactive session at a given +point; allowing you to script any preparation steps, then come back once it's +done. + +The ``--dump-design`` option +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Yosys provides the ``--dump-design`` option (or ``-P`` for short) for dumping +the design at specific steps of the script based on the log header. If the last +step before an error is ``7.2. Executing MEMORY_MAP pass (converting memories to +logic and flip-flops)``, then calling Yosys with ``--dump-design 7.2:bad.il`` +will save the design *before* this command runs, in the file ``bad.il``. + +It is also possible to use this option multiple times, e.g. ``-P2:hierarchy.il +-P7 -P7.2:bad.il``, to get multiple dumps in the same run. This can make it +easier to follow the design through each step to find where certain cells or +connections are coming from. ``--dump-design ALL`` is also allowed, writing out +the design at each log header. + +A worked example +~~~~~~~~~~~~~~~~ + +Say you did all the minimization and found that an error in `synth_xilinx` +occurs when a call to ``techmap -map +/xilinx/cells_map.v`` with +``MIN_MUX_INPUTS`` defined parses a `$_MUX16_` with all inputs set to ``1'x``. +You could fix the bug in ``+/xilinx/cells_map.v``, but that might only solve +this one case while leaving other problems that haven't been found yet. So you +step through the original script, calling `stat` after each step to find when +the `$_MUX16_` is added. + +You find that the `$_MUX16_` is introduced by a call to `muxcover`, but all the +inputs are defined, so calling `techmap` now works as expected. From running +`bugpoint` with the failing techmap you know that the cell with index ``2297`` +will fail, so you call ``select top/*$2297`` to limit to just that cell. This +can then be saved with ``design -save pre_bug`` or ``write_rtlil -selected +pre_bug.il``, so that you don't have to re-run all the earlier steps to get back +here. + +Next you step through the remaining commands and call `dump` after each to find +when the inputs are disconnected. You find that ``opt -full`` has optimized +away portions of the circuit, leading to `opt_expr` setting the undriven mux +inputs to ``x``, but failing to remove the now unnecessary `$_MUX16_`. Now +you've identified a problem in `opt_expr` that affects all of the wide muxes, +and could happen in any synthesis flow, not just `synth_xilinx`. + +.. seealso:: + + This example is taken from `YosysHQ/yosys#4590 + `_ and can be reproduced with a + version of Yosys between 0.45 and 0.51. diff --git a/docs/source/yosys_internals/extending_yosys/contributing.rst b/docs/source/yosys_internals/extending_yosys/contributing.rst index 69258aa5f..70170fc48 100644 --- a/docs/source/yosys_internals/extending_yosys/contributing.rst +++ b/docs/source/yosys_internals/extending_yosys/contributing.rst @@ -7,7 +7,7 @@ Contributing to Yosys |CONTRIBUTING|_ file. .. |CONTRIBUTING| replace:: :file:`CONTRIBUTING.md` -.. _CONTRIBUTING: https://github.com/YosysHQ/yosys/CONTRIBUTING.md +.. _CONTRIBUTING: https://github.com/YosysHQ/yosys/blob/main/CONTRIBUTING.md Coding Style ------------ @@ -42,3 +42,137 @@ for implicit type casts, always use ``GetSize(foobar)`` instead of ``foobar.size()``. (``GetSize()`` is defined in :file:`kernel/yosys.h`) Use range-based for loops whenever applicable. + + +Reporting bugs +-------------- + +- use the `bug report template`_ + +.. _bug report template: https://github.com/YosysHQ/yosys/issues/new?template=bug_report.yml + +- short title briefly describing the issue, e.g. + + techmap of wide mux with undefined inputs raises error during synth_xilinx + + + tells us what's happening ("raises error") + + gives the command affected (`techmap`) + + an overview of the input design ("wide mux with undefined inputs") + + and some context where it was found ("during `synth_xilinx`") + + +Reproduction Steps +~~~~~~~~~~~~~~~~~~ + +- ideally a code-block (starting and ending with triple backquotes) containing + the minimized design (Verilog or RTLIL), followed by a code-block containing + the minimized yosys script OR a command line call to yosys with + code-formatting (starting and ending with single backquotes) + +.. code-block:: markdown + + min.v + ```verilog + // minimized Verilog design + ``` + + min.ys + ``` + read_verilog min.v + # minimum sequence of commands to reproduce error + ``` + + OR + + `yosys -p ': minimum sequence of commands;' min.v` + +- alternatively can provide a single code-block which includes the minimized + design as a "here document" followed by the sequence of commands which + reproduce the error + + + see :doc:`/using_yosys/more_scripting/load_design` for more on heredocs. + +.. code-block:: markdown + + ``` + read_rtlil </path/to/file#L139-L147`` + + clicking on "Preview" should reveal a code block containing the lines of + source specified, with a link to the source file at the given commit + + +Additional details +~~~~~~~~~~~~~~~~~~ + +- once you have created the issue, any additional details can be added as a + comment on that issue +- could include any additional context as to what you were doing when you first + encountered the bug +- was this issue discovered through the use of a fuzzer +- if you've minimized the script, consider including the `bugpoint` script you + used, or the original script, e.g. + +.. code-block:: markdown + + Minimized with + ``` + read_verilog design.v + # original sequence of commands prior to error + bugpoint -script -grep "" + write_rtlil min.il + ``` + + OR + + Minimized from + `yosys -p ': original sequence of commands to produce error;' design.v` + +- if you're able to, it may also help to share the original un-minimized design + + + if the design is too big for a comment, consider turning it into a `Gist`_ + +.. _Gist: https://gist.github.com/ diff --git a/docs/source/yosys_internals/extending_yosys/index.rst b/docs/source/yosys_internals/extending_yosys/index.rst index 4ee21517b..72843ecd6 100644 --- a/docs/source/yosys_internals/extending_yosys/index.rst +++ b/docs/source/yosys_internals/extending_yosys/index.rst @@ -11,6 +11,7 @@ of interest for developers looking to customise Yosys builds. extensions build_verific functional_ir + advanced_bugpoint contributing test_suites diff --git a/docs/source/yosys_internals/hashing.rst b/docs/source/yosys_internals/hashing.rst index c6e22c0cf..b9608d99e 100644 --- a/docs/source/yosys_internals/hashing.rst +++ b/docs/source/yosys_internals/hashing.rst @@ -138,7 +138,7 @@ Previously, the interface to implement hashing on custom types was just independently and then ad-hoc combined with the hash function with some xorshift operations thrown in to mix bits together somewhat. A plugin can stay compatible with both versions prior and after the break by implementing both interfaces -based on the existance and value of `YS_HASHING_VERSION`. +based on the existance and value of ``YS_HASHING_VERSION``. .. code-block:: cpp :caption: Example hash compatibility wrapper diff --git a/docs/source/yosys_internals/index.rst b/docs/source/yosys_internals/index.rst index 3dd4224fa..483cc2bf8 100644 --- a/docs/source/yosys_internals/index.rst +++ b/docs/source/yosys_internals/index.rst @@ -38,5 +38,4 @@ as reference to implement a similar system in any language. formats/index extending_yosys/index techmap - verilog hashing diff --git a/docs/util/cellref.py b/docs/util/cell_documenter.py similarity index 100% rename from docs/util/cellref.py rename to docs/util/cell_documenter.py diff --git a/docs/util/cmd_documenter.py b/docs/util/cmd_documenter.py new file mode 100644 index 000000000..9347d8ffd --- /dev/null +++ b/docs/util/cmd_documenter.py @@ -0,0 +1,443 @@ +#!/usr/bin/env python3 +from __future__ import annotations + +from dataclasses import dataclass +import json +from pathlib import Path, PosixPath, WindowsPath +import re + +from typing import Any +from sphinx.application import Sphinx +from sphinx.ext import autodoc +from sphinx.ext.autodoc import Documenter +from sphinx.util import logging + +logger = logging.getLogger(__name__) + +# cmd signature +cmd_ext_sig_re = re.compile( + r'''^ ([\w/]+::)? # optional group + ([\w$._]+?) # module name + (?:\.([\w_]+))? # optional: thing name + (::[\w_]+)? # attribute + \s* $ # and nothing more + ''', re.VERBOSE) + +class YosysCmdContentListing: + type: str + body: str + source_file: str + source_line: int + options: dict[str, str] + content: list[YosysCmdContentListing] + + def __init__( + self, + type: str = "", + body: str = "", + source_file: str = "unknown", + source_line: int = 0, + options: dict[str, str] = {}, + content: list[dict[str]] = [], + ): + self.type = type + self.body = body + self.source_file = source_file + self.source_line = source_line + self.options = options + self.content = [YosysCmdContentListing(**c) for c in content] + +class YosysCmd: + name: str + title: str + content: list[YosysCmdContentListing] + group: str + source_file: str + source_line: int + source_func: str + experimental_flag: bool + internal_flag: bool + + def __init__( + self, + name:str = "", title:str = "", + content: list[dict[str]] = [], + group: str = 'unknown', + source_file: str = "", + source_line: int = 0, + source_func: str = "", + experimental_flag: bool = False, + internal_flag: bool = False, + ) -> None: + self.name = name + self.title = title + self.content = [YosysCmdContentListing(**c) for c in content] + self.group = group + self.source_file = source_file + self.source_line = source_line + self.source_func = source_func + self.experimental_flag = experimental_flag + self.internal_flag = internal_flag + +class YosysCmdGroupDocumenter(Documenter): + objtype = 'cmdgroup' + priority = 10 + object: tuple[str, list[str]] + lib_key = 'groups' + + option_spec = Documenter.option_spec.copy() + option_spec.update({ + 'caption': autodoc.annotation_option, + 'members': autodoc.members_option, + 'source': autodoc.bool_option, + 'linenos': autodoc.bool_option, + }) + + __cmd_lib: dict[str, list[str] | dict[str]] | None = None + @property + def cmd_lib(self) -> dict[str, list[str] | dict[str]]: + if not self.__cmd_lib: + self.__cmd_lib = {} + cmds_obj: dict[str, dict[str, dict[str]]] + try: + with open(self.config.cmds_json, "r") as f: + cmds_obj = json.loads(f.read()) + except FileNotFoundError: + logger.warning( + f"unable to find cmd lib at {self.config.cmds_json}", + type = 'cmdref', + subtype = 'cmd_lib' + ) + cmds_obj = {} + for (name, obj) in cmds_obj.get(self.lib_key, {}).items(): + self.__cmd_lib[name] = obj + return self.__cmd_lib + + @classmethod + def can_document_member( + cls, + member: Any, + membername: str, + isattr: bool, + parent: Any + ) -> bool: + return False + + def parse_name(self) -> bool: + if not self.options.caption: + self.content_indent = '' + self.fullname = self.modname = self.name + return True + + def import_object(self, raiseerror: bool = False) -> bool: + # get cmd + try: + self.object = (self.modname, self.cmd_lib[self.modname]) + except KeyError: + if raiseerror: + raise + return False + + self.real_modname = self.modname + return True + + def get_sourcename(self) -> str: + return self.env.doc2path(self.env.docname) + + def format_name(self) -> str: + return self.options.caption or '' + + def format_signature(self, **kwargs: Any) -> str: + return self.modname + + def add_directive_header(self, sig: str) -> None: + pass + + def add_content(self, more_content: Any | None) -> None: + pass + + def filter_members( + self, + members: list[tuple[str, Any]], + want_all: bool + ) -> list[tuple[str, Any, bool]]: + return [(x[0], x[1], False) for x in members] + + def get_object_members( + self, + want_all: bool + ) -> tuple[bool, list[tuple[str, Any]]]: + ret: list[tuple[str, str]] = [] + + if want_all: + for member in self.object[1]: + ret.append((member, self.modname)) + else: + memberlist = self.options.members or [] + for name in memberlist: + if name in self.object: + ret.append((name, self.modname)) + else: + logger.warning(('unknown module mentioned in :members: option: ' + f'group {self.modname}, module {name}'), + type='cmdref') + + return False, ret + + def document_members(self, all_members: bool = False) -> None: + want_all = (all_members or + self.options.inherited_members or + self.options.members is autodoc.ALL) + # find out which members are documentable + members_check_module, members = self.get_object_members(want_all) + + # document non-skipped members + memberdocumenters: list[tuple[Documenter, bool]] = [] + for (mname, member, isattr) in self.filter_members(members, want_all): + classes = [cls for cls in self.documenters.values() + if cls.can_document_member(member, mname, isattr, self)] + if not classes: + # don't know how to document this member + continue + # prefer the documenter with the highest priority + classes.sort(key=lambda cls: cls.priority) + # give explicitly separated module name, so that members + # of inner classes can be documented + full_mname = self.format_signature() + '::' + mname + documenter = classes[-1](self.directive, full_mname, self.indent) + memberdocumenters.append((documenter, isattr)) + + member_order = self.options.member_order or self.config.autodoc_member_order + memberdocumenters = self.sort_members(memberdocumenters, member_order) + + for documenter, isattr in memberdocumenters: + documenter.generate( + all_members=True, real_modname=self.real_modname, + check_module=members_check_module and not isattr) + + def generate( + self, + more_content: Any | None = None, + real_modname: str | None = None, + check_module: bool = False, + all_members: bool = False + ) -> None: + if not self.parse_name(): + # need a cmd lib to import from + logger.warning( + f"don't know which cmd lib to import for autodocumenting {self.name}", + type = 'cmdref' + ) + return + + sourcename = self.get_sourcename() + + imported_object = self.import_object(); + if self.lib_key == 'groups' and self.name == 'unknown': + if imported_object: + logger.warning(f"Found commands assigned to group {self.name}: {[x[0] for x in self.object]}", type='cmdref') + else: + return + elif not imported_object: + log_msg = f"unable to load {self.name} with {type(self)}" + if self.lib_key == 'groups': + logger.info(log_msg, type = 'cmdref') + self.add_line(f'.. warning:: No commands found for group {self.name!r}', sourcename) + self.add_line('', sourcename) + self.add_line(' Documentation may have been built without ``source_location`` support.', sourcename) + self.add_line(' Try check :doc:`/cmd/index_other`.', sourcename) + else: + logger.warning(log_msg, type = 'cmdref') + return + + # check __module__ of object (for members not given explicitly) + # if check_module: + # if not self.check_module(): + # return + + self.add_line('', sourcename) + + # format the object's signature, if any + try: + sig = self.format_signature() + except Exception as exc: + logger.warning(('error while formatting signature for %s: %s'), + self.fullname, exc, type='cmdref') + return + + # generate the directive header and options, if applicable + self.add_directive_header(sig) + self.add_line('', sourcename) + + # e.g. the module directive doesn't have content + self.indent += self.content_indent + + # add all content (from docstrings, attribute docs etc.) + self.add_content(more_content) + + # document members, if possible + self.document_members(all_members) + +class YosysCmdDocumenter(YosysCmdGroupDocumenter): + objtype = 'cmd' + priority = 15 + object: YosysCmd + lib_key = 'cmds' + + @classmethod + def can_document_member( + cls, + member: Any, + membername: str, + isattr: bool, + parent: Any + ) -> bool: + if membername.startswith('$'): + return False + return isinstance(parent, YosysCmdGroupDocumenter) + + def parse_name(self) -> bool: + try: + matched = cmd_ext_sig_re.match(self.name) + group, modname, thing, attribute = matched.groups() + except AttributeError: + logger.warning(('invalid signature for auto%s (%r)') % (self.objtype, self.name), + type='cmdref') + return False + + self.modname = modname + self.groupname = group or '' + self.attribute = attribute or '' + self.fullname = ((self.modname) + (thing or '')) + + return True + + def import_object(self, raiseerror: bool = False) -> bool: + if super().import_object(raiseerror): + self.object = YosysCmd(self.modname, **self.object[1]) + return True + return False + + def get_sourcename(self) -> str: + try: + return self.object.source_file + except AttributeError: + return super().get_sourcename() + + def format_name(self) -> str: + return self.object.name + + def format_signature(self, **kwargs: Any) -> str: + return self.fullname + self.attribute + + def add_directive_header(self, sig: str) -> None: + domain = getattr(self, 'domain', self.objtype) + directive = getattr(self, 'directivetype', 'def') + source_name = self.object.source_file + source_line = self.object.source_line + + title = f'{self.object.name} - {self.object.title}' + self.add_line(title, source_name, source_line) + self.add_line('#' * len(title), source_name, source_line) + + # cmd definition + self.add_line(f'.. {domain}:{directive}:: {sig}', source_name, source_line) + if self.object.title: + self.add_line(f' :title: {self.object.title}', source_name, source_line) + + if self.options.noindex: + self.add_line(' :noindex:', source_name) + + def add_content(self, more_content: Any | None) -> None: + # set sourcename and add content from attribute documentation + domain = getattr(self, 'domain', self.objtype) + source_name = self.object.source_file + source_line = self.object.source_line + + if self.object.experimental_flag: + self.add_line(f'.. warning:: This command is experimental', source_name, source_line) + self.add_line('\n', source_name) + + if self.object.internal_flag: + self.add_line(f'.. warning:: This command is intended for internal developer use only', source_name, source_line) + self.add_line('\n', source_name) + + def render(content_list: YosysCmdContentListing, indent: int=0): + content_source = content_list.source_file or source_name + indent_str = ' '*indent + if content_list.type == 'usage': + if content_list.body: + self.add_line(f'{indent_str}.. {domain}:{content_list.type}:: {self.name}::{content_list.body}', content_source) + else: + self.add_line(f'{indent_str}.. {domain}:{content_list.type}:: {self.name}::', content_source) + self.add_line(f'{indent_str} :noindex:', source_name) + self.add_line('', source_name) + elif content_list.type == 'option': + self.add_line(f'{indent_str}:{content_list.type} {content_list.body}:', content_source) + elif content_list.type == 'text': + self.add_line(f'{indent_str}{content_list.body}', content_source) + self.add_line('', source_name) + elif content_list.type == 'code': + language_str = content_list.options.get('language', '') + self.add_line(f'{indent_str}.. code-block:: {language_str}', source_name) + self.add_line('', source_name) + for body_line in content_list.body.splitlines(): + self.add_line(f'{indent_str} {body_line}', content_source) + self.add_line('', source_name) + else: + logger.warning(f"unknown content type '{content_list.type}'") + for content in content_list.content: + render(content, indent+1) + + for content in self.object.content: + render(content) + + if self.get_sourcename() != 'unknown': + self.add_line('\n', source_name) + self.add_line(f'.. note:: Help text automatically generated from :file:`{source_name}:{source_line}`', source_name) + + # add additional content (e.g. from document), if present + if more_content: + for line, src in zip(more_content.data, more_content.items): + self.add_line(line, src[0], src[1]) + + def get_object_members( + self, + want_all: bool + ) -> tuple[bool, list[tuple[str, Any]]]: + + return False, [] + +class YosysCmdRstDocumenter(YosysCmdDocumenter): + objtype = 'cmd_rst' + priority = 0 + + @classmethod + def can_document_member(cls, *args) -> bool: + return False + + def add_directive_header(self, sig): + source_name = self.object.source_file + cmd = self.object.name + self.add_line(f'.. code-block:: rst', source_name) + self.add_line(f' :caption: Generated rst for ``.. autocmd:: {cmd}``', source_name) + + def add_content(self, more_content): + source_name = self.object.source_file + cmd = self.object.name + self.domain = 'cmd' + super().add_directive_header(cmd) + self.add_line('', source_name) + self.indent += self.content_indent + super().add_content(more_content) + +def setup(app: Sphinx) -> dict[str, Any]: + app.add_config_value('cmds_json', False, 'html', [Path, PosixPath, WindowsPath]) + app.setup_extension('sphinx.ext.autodoc') + app.add_autodocumenter(YosysCmdGroupDocumenter) + app.add_autodocumenter(YosysCmdDocumenter) + app.add_autodocumenter(YosysCmdRstDocumenter) + return { + 'version': '2', + 'parallel_read_safe': True, + } diff --git a/docs/util/cmdref.py b/docs/util/custom_directives.py similarity index 81% rename from docs/util/cmdref.py rename to docs/util/custom_directives.py index a31b08e0d..b90584aa7 100644 --- a/docs/util/cmdref.py +++ b/docs/util/custom_directives.py @@ -4,20 +4,21 @@ from __future__ import annotations import re from typing import cast +import warnings from docutils import nodes -from docutils.nodes import Node, Element, system_message +from docutils.nodes import Node, Element, Text from docutils.parsers.rst import directives from docutils.parsers.rst.states import Inliner from sphinx.application import Sphinx from sphinx.domains import Domain, Index from sphinx.domains.std import StandardDomain from sphinx.environment import BuildEnvironment -from sphinx.roles import XRefRole +from sphinx.roles import XRefRole, SphinxRole from sphinx.directives import ObjectDescription from sphinx.directives.code import container_wrapper from sphinx.util.nodes import make_refnode -from sphinx.util.docfields import Field +from sphinx.util.docfields import Field, GroupedField from sphinx import addnodes class TocNode(ObjectDescription): @@ -31,7 +32,7 @@ class TocNode(ObjectDescription): signode['ids'].append(idx) def _object_hierarchy_parts(self, sig_node: addnodes.desc_signature) -> tuple[str, ...]: - if 'fullname' not in sig_node: + if 'tocname' not in sig_node: return () modname = sig_node.get('module') @@ -57,16 +58,56 @@ class TocNode(ObjectDescription): return '.'.join(parents + [name]) return '' -class CommandNode(TocNode): +class NodeWithOptions(TocNode): + """A custom node with options.""" + + doc_field_types = [ + GroupedField('opts', label='Options', names=('option', 'options', 'opt', 'opts')), + ] + + def transform_content(self, contentnode: addnodes.desc_content) -> None: + """hack `:option -thing: desc` into a proper option list with yoscrypt highlighting""" + newchildren = [] + for node in contentnode: + newnode = node + if isinstance(node, nodes.field_list): + newnode = nodes.option_list() + for field in node: + is_option = False + option_list_item = nodes.option_list_item() + for child in field: + if isinstance(child, nodes.field_name): + option_group = nodes.option_group() + option_list_item += option_group + option = nodes.option() + option_group += option + name, text = child.rawsource.split(' ', 1) + is_option = name == 'option' + literal = nodes.literal(text=text) + literal['classes'] += ['code', 'highlight', 'yoscrypt'] + literal['language'] = 'yoscrypt' + option += literal + if not is_option: warnings.warn(f'unexpected option \'{name}\' in {field.source}') + elif isinstance(child, nodes.field_body): + description = nodes.description() + description += child.children + option_list_item += description + if is_option: + newnode += option_list_item + newchildren.append(newnode) + contentnode.children = newchildren + +class CommandNode(NodeWithOptions): """A custom node that describes a command.""" name = 'cmd' required_arguments = 1 - option_spec = { + option_spec = NodeWithOptions.option_spec.copy() + option_spec.update({ 'title': directives.unchanged, 'tags': directives.unchanged - } + }) def handle_signature(self, sig, signode: addnodes.desc_signature): signode['fullname'] = sig @@ -93,6 +134,46 @@ class CommandNode(TocNode): idx, 0)) +class CommandUsageNode(NodeWithOptions): + """A custom node that describes command usages""" + + name = 'cmdusage' + + option_spec = NodeWithOptions.option_spec + option_spec.update({ + 'usage': directives.unchanged, + }) + + def handle_signature(self, sig: str, signode: addnodes.desc_signature): + parts = sig.split('::') + if len(parts) > 2: parts.pop(0) + use = parts[-1] + signode['fullname'] = '::'.join(parts) + usage = self.options.get('usage', use) + if usage: + signode['tocname'] = usage + signode += addnodes.desc_name(text=usage) + return signode['fullname'] + + def add_target_and_index( + self, + name: str, + sig: str, + signode: addnodes.desc_signature + ) -> None: + idx = ".".join(name.split("::")) + signode['ids'].append(idx) + if 'noindex' not in self.options: + tocname: str = signode.get('tocname', name) + objs = self.env.domaindata[self.domain]['objects'] + # (name, sig, typ, docname, anchor, prio) + objs.append((name, + tocname, + type(self).name, + self.env.docname, + idx, + 1)) + class PropNode(TocNode): name = 'prop' fieldname = 'props' @@ -393,7 +474,7 @@ class TagIndex(Index): lis.append(( dispname, 0, docname, anchor, - docname, '', typ + '', '', '' )) ret = [(k, v) for k, v in sorted(content.items())] @@ -432,18 +513,19 @@ class CommandIndex(Index): Qualifier and description are not rendered e.g. in LaTeX output. """ - content = {} + content: dict[str, list[tuple]] = {} items = ((name, dispname, typ, docname, anchor) for name, dispname, typ, docname, anchor, prio in self.domain.get_objects() if typ == self.name) items = sorted(items, key=lambda item: item[0]) for name, dispname, typ, docname, anchor in items: + title = self.domain.data['obj2title'].get(name) lis = content.setdefault(self.shortname, []) lis.append(( dispname, 0, docname, anchor, - '', '', typ + '', '', title )) ret = [(k, v) for k, v in sorted(content.items())] @@ -507,16 +589,27 @@ class PropIndex(TagIndex): return (ret, True) +class TitleRefRole(XRefRole): + """XRefRole used which has the cmd title as the displayed text.""" + pass + +class OptionRole(SphinxRole): + def run(self) -> tuple[list[Node], list]: + return self.inliner.interpreted(self.rawtext, self.text, 'yoscrypt', self.lineno) + class CommandDomain(Domain): name = 'cmd' label = 'Yosys commands' roles = { - 'ref': XRefRole() + 'ref': XRefRole(), + 'title': TitleRefRole(), + 'option': OptionRole(), } directives = { 'def': CommandNode, + 'usage': CommandUsageNode, } indices = { @@ -542,7 +635,7 @@ class CommandDomain(Domain): def resolve_xref(self, env, fromdocname, builder, typ, target, node, contnode): - + match = [(docname, anchor, name) for name, sig, typ, docname, anchor, prio in self.get_objects() if sig == target] @@ -552,9 +645,17 @@ class CommandDomain(Domain): targ = match[0][1] qual_name = match[0][2] title = self.data['obj2title'].get(qual_name, targ) - - return make_refnode(builder,fromdocname,todocname, - targ, contnode, title) + + if typ == 'title': + # caller wants the title in the content of the node + cmd = contnode.astext() + contnode = Text(f'{cmd} - {title}') + return make_refnode(builder, fromdocname, todocname, + targ, contnode) + else: + # cmd title as hover text + return make_refnode(builder, fromdocname, todocname, + targ, contnode, title) else: print(f"Missing ref for {target} in {fromdocname} ") return None @@ -592,10 +693,18 @@ class CellDomain(CommandDomain): def autoref(name, rawtext: str, text: str, lineno, inliner: Inliner, options=None, content=None): - role = 'cell:ref' if text[0] == '$' else 'cmd:ref' - if text.startswith("help ") and text.count(' ') == 1: - _, cmd = text.split(' ', 1) - text = f'{text} <{cmd}>' + words = text.split(' ') + if len(words) == 2 and words[0] == "help": + IsLinkable = True + thing = words[1] + else: + IsLinkable = len(words) == 1 and words[0][0] != '-' + thing = words[0] + if IsLinkable: + role = 'cell:ref' if thing[0] == '$' else 'cmd:ref' + text = f'{text} <{thing}>' + else: + role = 'yoscrypt' return inliner.interpreted(rawtext, text, role, lineno) def setup(app: Sphinx): @@ -622,4 +731,7 @@ def setup(app: Sphinx): app.add_role('autoref', autoref) - return {'version': '0.2'} + return { + 'version': '0.3', + 'parallel_read_safe': False, + } diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 05621d857..4d8c57ced 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1759,7 +1759,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin break; if (type == AST_GENBLOCK) break; - if (type == AST_CELLARRAY && children[i]->type == AST_CELL) + if (type == AST_CELLARRAY && (children[i]->type == AST_CELL || children[i]->type == AST_PRIMITIVE)) continue; if (type == AST_BLOCK && !str.empty()) break; @@ -2752,6 +2752,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (new_cell->type == AST_PRIMITIVE) { input_error("Cell arrays of primitives are currently not supported.\n"); } else { + this->dumpAst(NULL, " "); log_assert(new_cell->children.at(0)->type == AST_CELLTYPE); new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str.c_str()); } diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index d83db3410..7284c7cd9 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -123,7 +123,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil msg_type == VERIFIC_IGNORE ? "IGNORE" : msg_type == VERIFIC_INFO ? "INFO" : msg_type == VERIFIC_COMMENT ? "COMMENT" : - msg_type == VERIFIC_PROGRAM_ERROR ? "PROGRAM_ERROR" : "UNKNOWN", message_id); + msg_type == VERIFIC_PROGRAM_ERROR ? "PROGRAM_ERROR" : "UNKNOWN", message_id ? message_id : ""); string message = linefile ? stringf("%s:%d: ", LineFile::GetFileName(linefile), LineFile::GetLineNo(linefile)) : ""; message += vstringf(msg, args); @@ -2978,6 +2978,9 @@ std::set import_tops(const char* work, std::map args, RTLIL::Design *design) override { - static bool set_verific_global_flags = true; if (check_noverific_env()) log_cmd_error("This version of Yosys is built without Verific support.\n" @@ -4124,6 +4127,12 @@ struct VerificPass : public Pass { if (argidx > GetSize(args) && args[argidx].compare(0, 1, "-") == 0) cmd_error(args, argidx, "unknown option"); + if ((unsigned long)verific_sva_fsm_limit >= sizeof(1ull)*8) + log_cmd_error("-L %d: limit too large; maximum allowed value is %zu.\n", verific_sva_fsm_limit, sizeof(1ull)*8-1); + + if (already_imported) + log_warning("Note that all Verific flags were reset to defaults after last -import.\n"); + std::set top_mod_names; if (mode_all) @@ -4201,6 +4210,7 @@ struct VerificPass : public Pass { } verific_cleanup(); + already_imported = true; goto check_error; } diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 7652f8130..60d8292b8 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -479,14 +479,14 @@ struct SvaFsm GetSize(dnode.ctrl), verific_sva_fsm_limit); } - for (int i = 0; i < (1 << GetSize(dnode.ctrl)); i++) + for (unsigned long long i = 0; i < (1ull << GetSize(dnode.ctrl)); i++) { Const ctrl_val(i, GetSize(dnode.ctrl)); pool ctrl_bits; - for (int i = 0; i < GetSize(dnode.ctrl); i++) - if (ctrl_val[i] == State::S1) - ctrl_bits.insert(dnode.ctrl[i]); + for (int j = 0; j < GetSize(dnode.ctrl); j++) + if (ctrl_val[j] == State::S1) + ctrl_bits.insert(dnode.ctrl[j]); vector new_state; bool accept = false, cond = false; @@ -1616,7 +1616,7 @@ struct VerificSvaImporter inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION || (mode_cover && ( inst->Type() == PRIM_SVA_OVERLAPPED_FOLLOWED_BY || - inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION))) + inst->Type() == PRIM_SVA_NON_OVERLAPPED_FOLLOWED_BY))) { Net *antecedent_net = inst->GetInput1(); Net *consequent_net = inst->GetInput2(); diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 40162b8d3..e2d7a2cd9 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -112,6 +112,129 @@ static bool isUserType(std::string &s) return false; } +static bool is_hex_dig(char c, int *val) +{ + if ('0' <= c && c <= '9') { + *val = c - '0'; + return true; + } else if ('a' <= c && c <= 'f') { + *val = c - 'a' + 0xA; + return true; + } else if ('A' <= c && c <= 'F') { + *val = c - 'A' + 0xA; + return true; + } else if (c == 'x' || c == 'X' || c == 'z' || c == 'Z' || c == '?') { + log_file_warning(AST::current_filename.c_str(), frontend_verilog_yyget_lineno(), "'%c' not a valid digit in hex escape sequence.\n", c); + *val = 0; // not semantically valid in hex escape... + return true; // ...but still processed as part of hex token + } + + return false; +} + +static bool is_oct_dig(char c, int *val) +{ + if ('0' <= c && c <= '7') { + *val = c - '0'; + return true; + } else if (c == 'x' || c == 'X' || c == 'z' || c == 'Z' || c == '?') { + log_file_warning(AST::current_filename.c_str(), frontend_verilog_yyget_lineno(), "'%c' not a valid digit in octal escape sequence.\n", c); + *val = 0; // not semantically valid in octal escape... + return true; // ...but still processed as part of octal token + } + + return false; +} + +static std::string *process_str(char *str, int len, bool triple) +{ + char *in, *out; // Overwrite input buffer: flex manual states "Actions + // are free to modify 'yytext' except for lengthening it". + + for (in = str, out = str; in < str + len; in++) + switch (*in) { + case '\n': + case '\r': + if (in + 1 < str + len && (in[1] ^ *in) == ('\n' ^ '\r')) + in++; + if (!triple) + log_file_warning(AST::current_filename.c_str(), frontend_verilog_yyget_lineno(), "Multi-line string literals should be triple-quoted or escaped.\n"); + *out++ = '\n'; + break; + case '\\': + in++; + log_assert(in < str + len); + switch (*in) { + case 'a': + *out++ = '\a'; + break; + case 'f': + *out++ = '\f'; + break; + case 'n': + *out++ = '\n'; + break; + case 'r': /* not part of IEEE-1800 2023, but seems + like a good idea to support it anyway */ + *out++ = '\r'; + break; + case 't': + *out++ = '\t'; + break; + case 'v': + *out++ = '\v'; + break; + case 'x': + int val; + if (in + 1 < str + len && is_hex_dig(in[1], &val)) { + *out = val; + in++; + if (in + 1 < str + len && is_hex_dig(in[1], &val)) { + *out = *out * 0x10 + val; + in++; + } + out++; + } else + log_file_warning(AST::current_filename.c_str(), frontend_verilog_yyget_lineno(), "ignoring invalid hex escape.\n"); + break; + case '\\': + *out++ = '\\'; + break; + case '"': + *out++ = '"'; + break; + case '\n': + case '\r': + if (in + 1 < str + len && (in[1] ^ *in) == ('\n' ^ '\r')) + in++; + break; + default: + if ('0' <= *in && *in <= '7') { + int val; + + *out = *in - '0'; + if (in + 1 < str + len && is_oct_dig(in[1], &val)) { + *out = *out * 010 + val; + in++; + if (in + 1 < str + len && is_oct_dig(in[1], &val)) { + if (*out >= 040) + log_file_warning(AST::current_filename.c_str(), frontend_verilog_yyget_lineno(), "octal escape exceeds \\377\n"); + *out = *out * 010 + val; + in++; + } + } + out++; + } else + *out++ = *in; + } + break; + default: + *out++ = *in; + } + + return new std::string(str, out - str); +} + %} %option yylineno @@ -122,7 +245,6 @@ static bool isUserType(std::string &s) %option prefix="frontend_verilog_yy" %x COMMENT -%x STRING %x SYNOPSYS_TRANSLATE_OFF %x SYNOPSYS_FLAGS %x IMPORT_DPI @@ -335,47 +457,9 @@ TIME_SCALE_SUFFIX [munpf]?s return TOK_REALVAL; } -\" { BEGIN(STRING); } -([^\\"]|\\.)+ { yymore(); real_location = old_location; } -\" { - BEGIN(0); - char *yystr = strdup(yytext); - yystr[strlen(yytext) - 1] = 0; - int i = 0, j = 0; - while (yystr[i]) { - if (yystr[i] == '\\' && yystr[i + 1]) { - i++; - if (yystr[i] == 'a') - yystr[i] = '\a'; - else if (yystr[i] == 'f') - yystr[i] = '\f'; - else if (yystr[i] == 'n') - yystr[i] = '\n'; - else if (yystr[i] == 'r') - yystr[i] = '\r'; - else if (yystr[i] == 't') - yystr[i] = '\t'; - else if (yystr[i] == 'v') - yystr[i] = '\v'; - else if ('0' <= yystr[i] && yystr[i] <= '7') { - yystr[i] = yystr[i] - '0'; - if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { - yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0'; - i++; - } - if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { - yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0'; - i++; - } - } - } - yystr[j++] = yystr[i++]; - } - yystr[j] = 0; - yylval->string = new std::string(yystr, j); - free(yystr); - return TOK_STRING; -} +\"([^\\"]|\\.|\\\n)*\" { yylval->string = process_str(yytext + 1, yyleng - 2, false); return TOK_STRING; } + +\"{3}(\"{0,2}([^\\"]|\\.|\\\n))*\"{3} { yylval->string = process_str(yytext + 3, yyleng - 6, true); return TOK_STRING; } and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 { yylval->string = new std::string(yytext); diff --git a/kernel/constids.inc b/kernel/constids.inc index c77a25c01..29872d45e 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -286,3 +286,4 @@ X(A_WIDTHS) X(B_WIDTHS) X(C_WIDTHS) X(C_SIGNED) +X(raise_error) diff --git a/kernel/functional.cc b/kernel/functional.cc index adf7bfb0c..211527926 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -518,10 +518,13 @@ public: if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($check))) queue.emplace_back(cell); } - for (auto wire : module->wires()) { - if (wire->port_input) + // we are relying here on unsorted pools iterating last-in-first-out + for (auto riter = module->ports.rbegin(); riter != module->ports.rend(); ++riter) { + auto *wire = module->wire(*riter); + if (wire && wire->port_input) { factory.add_input(wire->name, ID($input), Sort(wire->width)); - if (wire->port_output) { + } + if (wire && wire->port_output) { auto &output = factory.add_output(wire->name, ID($output), Sort(wire->width)); output.set_value(enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width)))); } diff --git a/kernel/hashlib.h b/kernel/hashlib.h index 4144d701d..52ff96028 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -451,16 +451,21 @@ class dict { return 1; } - int do_lookup(const K &key, Hasher::hash_t &hash) const + int do_lookup(const K &key, Hasher::hash_t &hash) { if (hashtable.empty()) return -1; if (entries.size() * hashtable_size_trigger > hashtable.size()) { - ((dict*)this)->do_rehash(); + do_rehash(); hash = do_hash(key); } + return do_lookup_internal(key, hash); + } + + int do_lookup_internal(const K &key, Hasher::hash_t hash) const + { int index = hashtable[hash]; while (index >= 0 && !ops.cmp(entries[index].udata.first, key)) { @@ -471,6 +476,14 @@ class dict { return index; } + int do_lookup_no_rehash(const K &key, Hasher::hash_t hash) const + { + if (hashtable.empty()) + return -1; + + return do_lookup_internal(key, hash); + } + int do_insert(const K &key, Hasher::hash_t &hash) { if (hashtable.empty()) { @@ -694,14 +707,14 @@ public: int count(const K &key) const { Hasher::hash_t hash = do_hash(key); - int i = do_lookup(key, hash); + int i = do_lookup_no_rehash(key, hash); return i < 0 ? 0 : 1; } int count(const K &key, const_iterator it) const { Hasher::hash_t hash = do_hash(key); - int i = do_lookup(key, hash); + int i = do_lookup_no_rehash(key, hash); return i < 0 || i > it.index ? 0 : 1; } @@ -717,7 +730,7 @@ public: const_iterator find(const K &key) const { Hasher::hash_t hash = do_hash(key); - int i = do_lookup(key, hash); + int i = do_lookup_no_rehash(key, hash); if (i < 0) return end(); return const_iterator(this, i); @@ -735,7 +748,7 @@ public: const T& at(const K &key) const { Hasher::hash_t hash = do_hash(key); - int i = do_lookup(key, hash); + int i = do_lookup_no_rehash(key, hash); if (i < 0) throw std::out_of_range("dict::at()"); return entries[i].udata.second; @@ -744,7 +757,7 @@ public: const T& at(const K &key, const T &defval) const { Hasher::hash_t hash = do_hash(key); - int i = do_lookup(key, hash); + int i = do_lookup_no_rehash(key, hash); if (i < 0) return defval; return entries[i].udata.second; @@ -906,16 +919,21 @@ protected: return 1; } - int do_lookup(const K &key, Hasher::hash_t &hash) const + int do_lookup(const K &key, Hasher::hash_t &hash) { if (hashtable.empty()) return -1; if (entries.size() * hashtable_size_trigger > hashtable.size()) { - ((pool*)this)->do_rehash(); + do_rehash(); hash = do_hash(key); } + return do_lookup_internal(key, hash); + } + + int do_lookup_internal(const K &key, Hasher::hash_t hash) const + { int index = hashtable[hash]; while (index >= 0 && !ops.cmp(entries[index].udata, key)) { @@ -926,6 +944,14 @@ protected: return index; } + int do_lookup_no_rehash(const K &key, Hasher::hash_t hash) const + { + if (hashtable.empty()) + return -1; + + return do_lookup_internal(key, hash); + } + int do_insert(const K &value, Hasher::hash_t &hash) { if (hashtable.empty()) { @@ -1087,14 +1113,14 @@ public: int count(const K &key) const { Hasher::hash_t hash = do_hash(key); - int i = do_lookup(key, hash); + int i = do_lookup_no_rehash(key, hash); return i < 0 ? 0 : 1; } int count(const K &key, const_iterator it) const { Hasher::hash_t hash = do_hash(key); - int i = do_lookup(key, hash); + int i = do_lookup_no_rehash(key, hash); return i < 0 || i > it.index ? 0 : 1; } @@ -1110,7 +1136,7 @@ public: const_iterator find(const K &key) const { Hasher::hash_t hash = do_hash(key); - int i = do_lookup(key, hash); + int i = do_lookup_no_rehash(key, hash); if (i < 0) return end(); return const_iterator(this, i); @@ -1222,7 +1248,7 @@ public: int at(const K &key) const { Hasher::hash_t hash = database.do_hash(key); - int i = database.do_lookup(key, hash); + int i = database.do_lookup_no_rehash(key, hash); if (i < 0) throw std::out_of_range("idict::at()"); return i + offset; @@ -1231,7 +1257,7 @@ public: int at(const K &key, int defval) const { Hasher::hash_t hash = database.do_hash(key); - int i = database.do_lookup(key, hash); + int i = database.do_lookup_no_rehash(key, hash); if (i < 0) return defval; return i + offset; @@ -1240,7 +1266,7 @@ public: int count(const K &key) const { Hasher::hash_t hash = database.do_hash(key); - int i = database.do_lookup(key, hash); + int i = database.do_lookup_no_rehash(key, hash); return i < 0 ? 0 : 1; } diff --git a/kernel/io.cc b/kernel/io.cc index d7d126c4c..9811919ba 100644 --- a/kernel/io.cc +++ b/kernel/io.cc @@ -384,4 +384,125 @@ std::string escape_filename_spaces(const std::string& filename) return out; } +void format_emit_unescaped(std::string &result, std::string_view fmt) +{ + result.reserve(result.size() + fmt.size()); + for (size_t i = 0; i < fmt.size(); ++i) { + char ch = fmt[i]; + result.push_back(ch); + if (ch == '%' && i + 1 < fmt.size() && fmt[i + 1] == '%') { + ++i; + } + } +} + +std::string unescape_format_string(std::string_view fmt) +{ + std::string result; + format_emit_unescaped(result, fmt); + return result; +} + +static std::string string_view_stringf(std::string_view spec, ...) +{ + va_list ap; + va_start(ap, spec); + std::string result = vstringf(std::string(spec).c_str(), ap); + va_end(ap); + return result; +} + +template +static void format_emit_stringf(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, Arg arg) +{ + // Delegate nontrivial formats to the C library. + switch (num_dynamic_ints) { + case DynamicIntCount::NONE: + result += string_view_stringf(spec, arg); + return; + case DynamicIntCount::ONE: + result += string_view_stringf(spec, dynamic_ints[0], arg); + return; + case DynamicIntCount::TWO: + result += string_view_stringf(spec, dynamic_ints[0], dynamic_ints[1], arg); + return; + } + YOSYS_ABORT("Internal error"); +} + +void format_emit_long_long(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, long long arg) +{ + if (spec == "%d") { + // Format checking will have guaranteed num_dynamic_ints == 0. + result += std::to_string(static_cast(arg)); + return; + } + format_emit_stringf(result, spec, dynamic_ints, num_dynamic_ints, arg); +} + +void format_emit_unsigned_long_long(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, unsigned long long arg) +{ + if (spec == "%u") { + // Format checking will have guaranteed num_dynamic_ints == 0. + result += std::to_string(static_cast(arg)); + return; + } + if (spec == "%c") { + result += static_cast(arg); + return; + } + format_emit_stringf(result, spec, dynamic_ints, num_dynamic_ints, arg); +} + +void format_emit_double(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, double arg) +{ + format_emit_stringf(result, spec, dynamic_ints, num_dynamic_ints, arg); +} + +void format_emit_char_ptr(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, const char *arg) +{ + if (spec == "%s") { + // Format checking will have guaranteed num_dynamic_ints == 0. + result += arg; + return; + } + format_emit_stringf(result, spec, dynamic_ints, num_dynamic_ints, arg); +} + +void format_emit_string(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, const std::string &arg) +{ + if (spec == "%s") { + // Format checking will have guaranteed num_dynamic_ints == 0. + result += arg; + return; + } + format_emit_stringf(result, spec, dynamic_ints, num_dynamic_ints, arg.c_str()); +} + +void format_emit_string_view(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, std::string_view arg) +{ + if (spec == "%s") { + // Format checking will have guaranteed num_dynamic_ints == 0. + // We can output the string without creating a temporary copy. + result += arg; + return; + } + // Delegate nontrivial formats to the C library. We need to construct + // a temporary string to ensure null termination. + format_emit_stringf(result, spec, dynamic_ints, num_dynamic_ints, std::string(arg).c_str()); +} + +void format_emit_void_ptr(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, const void *arg) +{ + format_emit_stringf(result, spec, dynamic_ints, num_dynamic_ints, arg); +} + YOSYS_NAMESPACE_END diff --git a/kernel/io.h b/kernel/io.h index 91699d775..dafef8bfa 100644 --- a/kernel/io.h +++ b/kernel/io.h @@ -1,5 +1,6 @@ #include #include +#include #include "kernel/yosys_common.h" #ifndef YOSYS_IO_H @@ -50,18 +51,391 @@ inline std::string vstringf(const char *fmt, va_list ap) #endif } -std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2)); - -inline std::string stringf(const char *fmt, ...) +enum ConversionSpecifier : uint8_t { - std::string string; - va_list ap; + CONVSPEC_NONE, + // Specifier not understood/supported + CONVSPEC_ERROR, + // Consumes a "long long" + CONVSPEC_SIGNED_INT, + // Consumes a "unsigned long long" + CONVSPEC_UNSIGNED_INT, + // Consumes a "double" + CONVSPEC_DOUBLE, + // Consumes a "const char*" or other string type + CONVSPEC_CHAR_PTR, + // Consumes a "void*" + CONVSPEC_VOID_PTR, +}; - va_start(ap, fmt); - string = vstringf(fmt, ap); - va_end(ap); +constexpr ConversionSpecifier parse_conversion_specifier(char ch, char prev_ch) +{ + switch (ch) { + case 'd': + case 'i': + return CONVSPEC_SIGNED_INT; + case 'o': + case 'u': + case 'x': + case 'X': + case 'm': + return CONVSPEC_UNSIGNED_INT; + case 'c': + if (prev_ch == 'l' || prev_ch == 'q' || prev_ch == 'L') { + // wchar not supported + return CONVSPEC_ERROR; + } + return CONVSPEC_UNSIGNED_INT; + case 'e': + case 'E': + case 'f': + case 'F': + case 'g': + case 'G': + case 'a': + case 'A': + return CONVSPEC_DOUBLE; + case 's': + if (prev_ch == 'l' || prev_ch == 'q' || prev_ch == 'L') { + // wchar not supported + return CONVSPEC_ERROR; + } + return CONVSPEC_CHAR_PTR; + case 'p': + return CONVSPEC_VOID_PTR; + case '$': // positional parameters + case 'n': + case 'S': + return CONVSPEC_ERROR; + default: + return CONVSPEC_NONE; + } +} - return string; +enum class DynamicIntCount : uint8_t { + NONE = 0, + ONE = 1, + TWO = 2, +}; + +// Describes a printf-style format conversion specifier found in a format string. +struct FoundFormatSpec +{ + // The start offset of the conversion spec in the format string. + int start; + // The end offset of the conversion spec in the format string. + int end; + ConversionSpecifier spec; + // Number of int args consumed by '*' dynamic width/precision args. + DynamicIntCount num_dynamic_ints; +}; + +// Ensure there is no format spec. +constexpr void ensure_no_format_spec(std::string_view fmt, int index, bool *has_escapes) +{ + int fmt_size = static_cast(fmt.size()); + // A trailing '%' is not a format spec. + while (index + 1 < fmt_size) { + if (fmt[index] != '%') { + ++index; + continue; + } + if (fmt[index + 1] != '%') { + YOSYS_ABORT("More format conversion specifiers than arguments"); + } + *has_escapes = true; + index += 2; + } +} + +// Returns the next format conversion specifier (starting with '%'). +// Returns CONVSPEC_NONE if there isn't a format conversion specifier. +constexpr FoundFormatSpec find_next_format_spec(std::string_view fmt, int fmt_start, bool *has_escapes) +{ + int index = fmt_start; + int fmt_size = static_cast(fmt.size()); + while (index < fmt_size) { + if (fmt[index] != '%') { + ++index; + continue; + } + int p = index + 1; + uint8_t num_dynamic_ints = 0; + while (true) { + if (p == fmt_size) { + return {0, 0, CONVSPEC_NONE, DynamicIntCount::NONE}; + } + if (fmt[p] == '%') { + *has_escapes = true; + index = p + 1; + break; + } + if (fmt[p] == '*') { + if (num_dynamic_ints >= 2) { + return {0, 0, CONVSPEC_ERROR, DynamicIntCount::NONE}; + } + ++num_dynamic_ints; + } + ConversionSpecifier spec = parse_conversion_specifier(fmt[p], fmt[p - 1]); + if (spec != CONVSPEC_NONE) { + return {index, p + 1, spec, static_cast(num_dynamic_ints)}; + } + ++p; + } + } + return {0, 0, CONVSPEC_NONE, DynamicIntCount::NONE}; +} + +template +constexpr typename std::enable_if::type +check_format(std::string_view fmt, int fmt_start, bool *has_escapes, FoundFormatSpec*, DynamicIntCount) +{ + ensure_no_format_spec(fmt, fmt_start, has_escapes); +} + +// Check that the format string `fmt.substr(fmt_start)` is valid for the given type arguments. +// Fills `specs` with the FoundFormatSpecs found in the format string. +// `int_args_consumed` is the number of int arguments already consumed to satisfy the +// dynamic width/precision args for the next format conversion specifier. +template +constexpr void check_format(std::string_view fmt, int fmt_start, bool *has_escapes, FoundFormatSpec* specs, + DynamicIntCount int_args_consumed) +{ + FoundFormatSpec found = find_next_format_spec(fmt, fmt_start, has_escapes); + if (found.num_dynamic_ints > int_args_consumed) { + // We need to consume at least one more int for the dynamic + // width/precision of this format conversion specifier. + if constexpr (!std::is_convertible_v) { + YOSYS_ABORT("Expected dynamic int argument"); + } + check_format(fmt, fmt_start, has_escapes, specs, + static_cast(static_cast(int_args_consumed) + 1)); + return; + } + switch (found.spec) { + case CONVSPEC_NONE: + YOSYS_ABORT("Expected format conversion specifier for argument"); + break; + case CONVSPEC_ERROR: + YOSYS_ABORT("Found unsupported format conversion specifier"); + break; + case CONVSPEC_SIGNED_INT: + if constexpr (!std::is_convertible_v) { + YOSYS_ABORT("Expected type convertible to signed integer"); + } + *specs = found; + break; + case CONVSPEC_UNSIGNED_INT: + if constexpr (!std::is_convertible_v) { + YOSYS_ABORT("Expected type convertible to unsigned integer"); + } + *specs = found; + break; + case CONVSPEC_DOUBLE: + if constexpr (!std::is_convertible_v) { + YOSYS_ABORT("Expected type convertible to double"); + } + *specs = found; + break; + case CONVSPEC_CHAR_PTR: + if constexpr (!std::is_convertible_v && + !std::is_convertible_v && + !std::is_convertible_v) { + YOSYS_ABORT("Expected type convertible to char *"); + } + *specs = found; + break; + case CONVSPEC_VOID_PTR: + if constexpr (!std::is_convertible_v) { + YOSYS_ABORT("Expected pointer type"); + } + *specs = found; + break; + } + check_format(fmt, found.end, has_escapes, specs + 1, DynamicIntCount::NONE); +} + +// Emit the string representation of `arg` that has been converted to a `long long'. +void format_emit_long_long(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, long long arg); + +// Emit the string representation of `arg` that has been converted to a `unsigned long long'. +void format_emit_unsigned_long_long(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, unsigned long long arg); + +// Emit the string representation of `arg` that has been converted to a `double'. +void format_emit_double(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, double arg); + +// Emit the string representation of `arg` that has been converted to a `const char*'. +void format_emit_char_ptr(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, const char *arg); + +// Emit the string representation of `arg` that has been converted to a `std::string'. +void format_emit_string(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, const std::string &arg); + +// Emit the string representation of `arg` that has been converted to a `std::string_view'. +void format_emit_string_view(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, std::string_view arg); + +// Emit the string representation of `arg` that has been converted to a `double'. +void format_emit_void_ptr(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, const void *arg); + +// Emit the string representation of `arg` according to the given `FoundFormatSpec`, +// appending it to `result`. +template +inline void format_emit_one(std::string &result, std::string_view fmt, const FoundFormatSpec &ffspec, + int *dynamic_ints, const Arg& arg) +{ + std::string_view spec = fmt.substr(ffspec.start, ffspec.end - ffspec.start); + DynamicIntCount num_dynamic_ints = ffspec.num_dynamic_ints; + switch (ffspec.spec) { + case CONVSPEC_SIGNED_INT: + if constexpr (std::is_convertible_v) { + long long s = arg; + format_emit_long_long(result, spec, dynamic_ints, num_dynamic_ints, s); + return; + } + break; + case CONVSPEC_UNSIGNED_INT: + if constexpr (std::is_convertible_v) { + unsigned long long s = arg; + format_emit_unsigned_long_long(result, spec, dynamic_ints, num_dynamic_ints, s); + return; + } + break; + case CONVSPEC_DOUBLE: + if constexpr (std::is_convertible_v) { + double s = arg; + format_emit_double(result, spec, dynamic_ints, num_dynamic_ints, s); + return; + } + break; + case CONVSPEC_CHAR_PTR: + if constexpr (std::is_convertible_v) { + const char *s = arg; + format_emit_char_ptr(result, spec, dynamic_ints, num_dynamic_ints, s); + return; + } + if constexpr (std::is_convertible_v) { + const std::string &s = arg; + format_emit_string(result, spec, dynamic_ints, num_dynamic_ints, s); + return; + } + if constexpr (std::is_convertible_v) { + const std::string_view &s = arg; + format_emit_string_view(result, spec, dynamic_ints, num_dynamic_ints, s); + return; + } + break; + case CONVSPEC_VOID_PTR: + if constexpr (std::is_convertible_v) { + const void *s = arg; + format_emit_void_ptr(result, spec, dynamic_ints, num_dynamic_ints, s); + return; + } + break; + default: + break; + } + YOSYS_ABORT("Internal error"); +} + +// Append the format string `fmt` to `result`, assuming there are no format conversion +// specifiers other than "%%" and therefore no arguments. Unescape "%%". +void format_emit_unescaped(std::string &result, std::string_view fmt); +std::string unescape_format_string(std::string_view fmt); + +inline void format_emit(std::string &result, std::string_view fmt, int fmt_start, + bool has_escapes, const FoundFormatSpec*, int*, DynamicIntCount) +{ + fmt = fmt.substr(fmt_start); + if (has_escapes) { + format_emit_unescaped(result, fmt); + } else { + result += fmt; + } +} +// Format `args` according to `fmt` (starting at `fmt_start`) and `specs` and append to `result`. +// `num_dynamic_ints` in `dynamic_ints[]` have already been collected to provide as +// dynamic width/precision args for the next format conversion specifier. +template +inline void format_emit(std::string &result, std::string_view fmt, int fmt_start, bool has_escapes, + const FoundFormatSpec* specs, int *dynamic_ints, DynamicIntCount num_dynamic_ints, + const Arg &arg, const Args &... args) +{ + if (specs->num_dynamic_ints > num_dynamic_ints) { + // Collect another int for the dynamic width precision/args + // for the next format conversion specifier. + if constexpr (std::is_convertible_v) { + dynamic_ints[static_cast(num_dynamic_ints)] = arg; + } else { + YOSYS_ABORT("Internal error"); + } + format_emit(result, fmt, fmt_start, has_escapes, specs, dynamic_ints, + static_cast(static_cast(num_dynamic_ints) + 1), args...); + return; + } + std::string_view str = fmt.substr(fmt_start, specs->start - fmt_start); + if (has_escapes) { + format_emit_unescaped(result, str); + } else { + result += str; + } + format_emit_one(result, fmt, *specs, dynamic_ints, arg); + format_emit(result, fmt, specs->end, has_escapes, specs + 1, dynamic_ints, DynamicIntCount::NONE, args...); +} + +template +inline std::string format_emit_toplevel(std::string_view fmt, bool has_escapes, const FoundFormatSpec* specs, const Args &... args) +{ + std::string result; + int dynamic_ints[2] = { 0, 0 }; + format_emit(result, fmt, 0, has_escapes, specs, dynamic_ints, DynamicIntCount::NONE, args...); + return result; +} +template <> +inline std::string format_emit_toplevel(std::string_view fmt, bool has_escapes, const FoundFormatSpec*) +{ + if (!has_escapes) { + return std::string(fmt); + } + return unescape_format_string(fmt); +} + +// This class parses format strings to build a list of `FoundFormatSpecs` in `specs`. +// When the compiler supports `consteval` (C++20), this parsing happens at compile time and +// type errors will be reported at compile time. Otherwise the parsing happens at +// runtime and type errors will trigger an `abort()` at runtime. +template +class FmtString +{ +public: + // Implicit conversion from const char * means that users can pass + // C string constants which are automatically parsed. + YOSYS_CONSTEVAL FmtString(const char *p) : fmt(p) + { + check_format(fmt, 0, &has_escapes, specs, DynamicIntCount::NONE); + } + std::string format(const Args &... args) + { + return format_emit_toplevel(fmt, has_escapes, specs, args...); + } +private: + std::string_view fmt; + bool has_escapes = false; + FoundFormatSpec specs[sizeof...(Args)] = {}; +}; + +template struct WrapType { using type = T; }; +template using TypeIdentity = typename WrapType::type; + +template +inline std::string stringf(FmtString...> fmt, Args... args) +{ + return fmt.format(args...); } int readsome(std::istream &f, char *s, int n); diff --git a/kernel/json.h b/kernel/json.h index c9aa0e045..e8905c8e1 100644 --- a/kernel/json.h +++ b/kernel/json.h @@ -90,10 +90,10 @@ public: template void array(const T &&values) { - begin_object(); + begin_array(); for (auto &item : values) value(item); - end_object(); + end_array(); } }; diff --git a/kernel/log.cc b/kernel/log.cc index fabbe09fd..679a55562 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -664,15 +664,9 @@ const char *log_const(const RTLIL::Const &value, bool autoint) const char *log_id(const RTLIL::IdString &str) { - log_id_cache.push_back(strdup(str.c_str())); - const char *p = log_id_cache.back(); - if (p[0] != '\\') - return p; - if (p[1] == '$' || p[1] == '\\' || p[1] == 0) - return p; - if (p[1] >= '0' && p[1] <= '9') - return p; - return p+1; + std::string unescaped = RTLIL::unescape_id(str); + log_id_cache.push_back(strdup(unescaped.c_str())); + return log_id_cache.back(); } const char *log_str(const char *str) diff --git a/kernel/log_help.cc b/kernel/log_help.cc new file mode 100644 index 000000000..30c06a7c3 --- /dev/null +++ b/kernel/log_help.cc @@ -0,0 +1,150 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2025 Krystine Dawn + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/log_help.h" + +USING_YOSYS_NAMESPACE + +Json ContentListing::to_json() const { + Json::object object; + object["type"] = type; + if (body.length()) object["body"] = body; + if (strcmp(source_file, "unknown") != 0) object["source_file"] = source_file; + if (source_line != 0) object["source_line"] = source_line; + object["options"] = Json(options); + Json::array content_array; + for (auto child : _content) content_array.push_back(child.to_json()); + object["content"] = content_array; + return object; +} + +void ContentListing::usage(const string &text, + const source_location location) +{ + log_assert(type.compare("root") == 0); + add_content("usage", text, location); +} + +void ContentListing::option(const string &text, const string &description, + const source_location location) +{ + auto option = open_option(text); + if (description.length()) + option->add_content("text", description, location); +} + +void ContentListing::codeblock(const string &code, const string &language, + const source_location location) +{ + add_content("code", code, location); + back()->set_option("language", language); +} + +void ContentListing::paragraph(const string &text, + const source_location location) +{ + add_content("text", text, location); +} + +ContentListing* ContentListing::open_usage(const string &text, + const source_location location) +{ + usage(text, location); + return back(); +} + +ContentListing* ContentListing::open_option(const string &text, + const source_location location) +{ + log_assert(type.compare("root") == 0 || type.compare("usage") == 0); + add_content("option", text, location); + return back(); +} + +#define MAX_LINE_LEN 80 +void log_pass_str(const std::string &pass_str, std::string indent_str, bool leading_newline=false) { + if (pass_str.empty()) + return; + std::istringstream iss(pass_str); + if (leading_newline) + log("\n"); + for (std::string line; std::getline(iss, line);) { + log("%s", indent_str.c_str()); + auto curr_len = indent_str.length(); + std::istringstream lss(line); + for (std::string word; std::getline(lss, word, ' ');) { + while (word[0] == '`' && word.back() == '`') + word = word.substr(1, word.length()-2); + if (curr_len + word.length() >= MAX_LINE_LEN-1) { + curr_len = 0; + log("\n%s", indent_str.c_str()); + } + if (word.length()) { + log("%s ", word.c_str()); + curr_len += word.length() + 1; + } + } + log("\n"); + } +} +void log_pass_str(const std::string &pass_str, int indent=0, bool leading_newline=false) { + std::string indent_str(indent*4, ' '); + log_pass_str(pass_str, indent_str, leading_newline); +} + +PrettyHelp *current_help = nullptr; + +PrettyHelp::PrettyHelp() +{ + _prior = current_help; + _root_listing = ContentListing("root", ""); + + current_help = this; +} + +PrettyHelp::~PrettyHelp() +{ + current_help = _prior; +} + +PrettyHelp *PrettyHelp::get_current() +{ + if (current_help == nullptr) + new PrettyHelp(); + return current_help; +} + +void PrettyHelp::log_help() const +{ + for (auto &content : _root_listing) { + if (content.type.compare("usage") == 0) { + log_pass_str(content.body, 1, true); + log("\n"); + } else if (content.type.compare("option") == 0) { + log_pass_str(content.body, 1); + for (auto text : content) { + log_pass_str(text.body, 2); + log("\n"); + } + } else { + log_pass_str(content.body, 0); + log("\n"); + } + } +} diff --git a/kernel/log_help.h b/kernel/log_help.h new file mode 100644 index 000000000..3ce0ac7aa --- /dev/null +++ b/kernel/log_help.h @@ -0,0 +1,128 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2025 Krystine Dawn + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef LOG_HELP_H +#define LOG_HELP_H + +#include "kernel/yosys_common.h" +#include "kernel/json.h" + +YOSYS_NAMESPACE_BEGIN + +class ContentListing { + vector _content; +public: + string type; + string body; + const char* source_file; + int source_line; + std::map options; + + ContentListing( + string type = "root", string body = "", + const char* source_file = "unknown", int source_line = 0 + ) : type(type), body(body), source_file(source_file), source_line(source_line) { + _content = {}; + options = {}; + } + + ContentListing(string type, string body, source_location location) : + ContentListing(type, body, location.file_name(), location.line()) { } + + void add_content(string type, string body, source_location location) { + _content.push_back({type, body, location}); + } + + bool has_content() const { return _content.size() != 0; } + + vector::const_iterator begin() const { return _content.cbegin(); } + vector::const_iterator end() const { return _content.cend(); } + + ContentListing* back() { + return &_content.back(); + } + + void set_option(string key, string val = "") { + options[key] = val; + } + + void usage( + const string &text, + const source_location location = source_location::current() + ); + void option( + const string &text, + const string &description = "", + const source_location location = source_location::current() + ); + void codeblock( + const string &code, + const string &language = "none", + const source_location location = source_location::current() + ); + void paragraph( + const string &text, + const source_location location = source_location::current() + ); + + ContentListing* open_usage( + const string &text, + const source_location location = source_location::current() + ); + ContentListing* open_option( + const string &text, + const source_location location = source_location::current() + ); + + Json to_json() const; +}; + +class PrettyHelp +{ +public: + string group = "unknown"; + +private: + PrettyHelp *_prior; + ContentListing _root_listing; + +public: + PrettyHelp(); + ~PrettyHelp(); + + static PrettyHelp *get_current(); + + bool has_content() const { return _root_listing.has_content(); } + + vector::const_iterator begin() const { return _root_listing.begin(); } + vector::const_iterator end() const { return _root_listing.end(); } + + ContentListing* get_root() { + return &_root_listing; + } + + void set_group(const string g) { group = g; } + bool has_group() const { return group.compare("unknown") != 0; } + + void log_help() const; +}; + +YOSYS_NAMESPACE_END + +#endif diff --git a/kernel/register.cc b/kernel/register.cc index af1823b5b..0b02a6aa5 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -21,6 +21,7 @@ #include "kernel/satgen.h" #include "kernel/json.h" #include "kernel/gzip.h" +#include "kernel/log_help.h" #include #include @@ -41,7 +42,8 @@ std::map backend_register; std::vector Frontend::next_args; -Pass::Pass(std::string name, std::string short_help) : pass_name(name), short_help(short_help) +Pass::Pass(std::string name, std::string short_help, source_location location) : + pass_name(name), short_help(short_help), location(location) { next_queued_pass = first_queued_pass; first_queued_pass = this; @@ -116,9 +118,19 @@ void Pass::post_execute(Pass::pre_post_exec_state_t state) void Pass::help() { - log("\n"); - log("No help message for command `%s'.\n", pass_name.c_str()); - log("\n"); + auto prettyHelp = PrettyHelp(); + if (formatted_help()) { + prettyHelp.log_help(); + } else { + log("\n"); + log("No help message for command `%s'.\n", pass_name.c_str()); + log("\n"); + } +} + +bool Pass::formatted_help() +{ + return false; } void Pass::clear_flags() @@ -381,8 +393,8 @@ void ScriptPass::help_script() script(); } -Frontend::Frontend(std::string name, std::string short_help) : - Pass(name.rfind("=", 0) == 0 ? name.substr(1) : "read_" + name, short_help), +Frontend::Frontend(std::string name, std::string short_help, source_location location) : + Pass(name.rfind("=", 0) == 0 ? name.substr(1) : "read_" + name, short_help, location), frontend_name(name.rfind("=", 0) == 0 ? name.substr(1) : name) { } @@ -527,8 +539,8 @@ void Frontend::frontend_call(RTLIL::Design *design, std::istream *f, std::string } } -Backend::Backend(std::string name, std::string short_help) : - Pass(name.rfind("=", 0) == 0 ? name.substr(1) : "write_" + name, short_help), +Backend::Backend(std::string name, std::string short_help, source_location location) : + Pass(name.rfind("=", 0) == 0 ? name.substr(1) : "write_" + name, short_help, location), backend_name(name.rfind("=", 0) == 0 ? name.substr(1) : name) { } @@ -681,6 +693,23 @@ static string get_cell_name(string name) { return is_code_getter(name) ? name.substr(0, name.length()-1) : name; } +static void log_warning_flags(Pass *pass) { + bool has_warnings = false; + const string name = pass->pass_name; + if (pass->experimental_flag) { + if (!has_warnings) log("\n"); + has_warnings = true; + log("WARNING: THE '%s' COMMAND IS EXPERIMENTAL.\n", name.c_str()); + } + if (pass->internal_flag) { + if (!has_warnings) log("\n"); + has_warnings = true; + log("WARNING: THE '%s' COMMAND IS INTENDED FOR INTERNAL DEVELOPER USE ONLY.\n", name.c_str()); + } + if (has_warnings) + log("\n"); +} + static struct CellHelpMessages { dict cell_help; CellHelpMessages() { @@ -706,155 +735,211 @@ struct HelpPass : public Pass { log(" help + .... print verilog code for given cell type\n"); log("\n"); } - void write_cmd_rst(std::string cmd, std::string title, std::string text) - { - FILE *f = fopen(stringf("docs/source/cmd/%s.rst", cmd.c_str()).c_str(), "wt"); - // make header - size_t char_len = cmd.length() + 3 + title.length(); - std::string title_line = "\n"; - title_line.insert(0, char_len, '='); - fprintf(f, "%s", title_line.c_str()); - fprintf(f, "%s - %s\n", cmd.c_str(), title.c_str()); - fprintf(f, "%s\n", title_line.c_str()); + bool dump_cmds_json(PrettyJson &json) { + // init json + json.begin_object(); + json.entry("version", "Yosys command reference"); + json.entry("generator", yosys_version_str); - // render html - fprintf(f, ".. cmd:def:: %s\n", cmd.c_str()); - fprintf(f, " :title: %s\n\n", title.c_str()); - fprintf(f, " .. only:: html\n\n"); - std::stringstream ss; - std::string textcp = text; - ss << text; - bool IsUsage = true; - int blank_count = 0; - size_t def_strip_count = 0; - bool WasDefinition = false; - for (std::string line; std::getline(ss, line, '\n');) { - // find position of first non space character - std::size_t first_pos = line.find_first_not_of(" \t"); - std::size_t last_pos = line.find_last_not_of(" \t"); - if (first_pos == std::string::npos) { - // skip formatting empty lines - if (!WasDefinition) - fputc('\n', f); - blank_count += 1; - continue; + bool raise_error = false; + std::map> groups; + + json.name("cmds"); json.begin_object(); + // iterate over commands + for (auto &it : pass_register) { + auto name = it.first; + auto pass = it.second; + auto title = pass->short_help; + + auto cmd_help = PrettyHelp(); + auto has_pretty_help = pass->formatted_help(); + + if (!has_pretty_help) { + enum PassUsageState { + PUState_none, + PUState_signature, + PUState_options, + PUState_optionbody, + }; + + source_location null_source; + string current_buffer = ""; + auto root_listing = cmd_help.get_root(); + auto current_listing = root_listing; + + // dump command help + std::ostringstream buf; + log_streams.push_back(&buf); + pass->help(); + log_streams.pop_back(); + std::stringstream ss; + ss << buf.str(); + + // parse command help + size_t def_strip_count = 0; + auto current_state = PUState_none; + auto catch_verific = false; + auto blank_lines = 2; + for (string line; std::getline(ss, line, '\n');) { + // find position of first non space character + std::size_t first_pos = line.find_first_not_of(" \t"); + std::size_t last_pos = line.find_last_not_of(" \t"); + if (first_pos == std::string::npos) { + switch (current_state) + { + case PUState_signature: + root_listing->usage(current_buffer, null_source); + current_listing = root_listing; + current_state = PUState_none; + current_buffer = ""; + break; + case PUState_none: + case PUState_optionbody: + blank_lines += 1; + break; + default: + break; + } + // skip empty lines + continue; + } + + // strip leading and trailing whitespace + std::string stripped_line = line.substr(first_pos, last_pos - first_pos +1); + bool IsDefinition = stripped_line[0] == '-'; + IsDefinition &= stripped_line[1] != ' ' && stripped_line[1] != '>'; + bool IsDedent = def_strip_count && first_pos < def_strip_count; + bool IsIndent = def_strip_count < first_pos; + + // line looks like a signature + bool IsSignature = stripped_line.find(name) == 0 && (stripped_line.length() == name.length() || stripped_line.at(name.size()) == ' '); + + if (IsSignature && first_pos <= 4 && (blank_lines >= 2 || current_state == PUState_signature)) { + if (current_state == PUState_options || current_state == PUState_optionbody) { + current_listing->codeblock(current_buffer, "none", null_source); + current_buffer = ""; + } else if (current_state == PUState_signature) { + root_listing->usage(current_buffer, null_source); + current_buffer = ""; + } else if (current_state == PUState_none && !current_buffer.empty()) { + current_listing->codeblock(current_buffer, "none", null_source); + current_buffer = ""; + } + current_listing = root_listing; + current_state = PUState_signature; + def_strip_count = first_pos; + catch_verific = false; + } else if (IsDedent) { + def_strip_count = first_pos; + if (current_state == PUState_optionbody) { + if (!current_buffer.empty()) { + current_listing->codeblock(current_buffer, "none", null_source); + current_buffer = ""; + } + if (IsIndent) { + current_state = PUState_options; + current_listing = root_listing->back(); + } else { + current_state = PUState_none; + current_listing = root_listing; + } + } else { + current_state = PUState_none; + } + } + + if (IsDefinition && !catch_verific && current_state != PUState_signature) { + if (!current_buffer.empty()) { + current_listing->codeblock(current_buffer, "none", null_source); + current_buffer = ""; + } + current_state = PUState_options; + current_listing = root_listing->open_option(stripped_line, null_source); + def_strip_count = first_pos; + } else { + if (current_state == PUState_options) { + current_state = PUState_optionbody; + } + if (current_buffer.empty()) + current_buffer = stripped_line; + else if (current_state == PUState_signature && IsIndent) + current_buffer += stripped_line; + else if (current_state == PUState_none) { + current_buffer += (blank_lines > 0 ? "\n\n" : "\n") + line; + } else + current_buffer += (blank_lines > 0 ? "\n\n" : "\n") + stripped_line; + if (stripped_line.compare("Command file parser supports following commands in file:") == 0) + catch_verific = true; + } + blank_lines = 0; + } + + if (!current_buffer.empty()) { + if (current_buffer.size() > 64 && current_buffer.substr(0, 64).compare("The following commands are executed by this synthesis command:\n\n") == 0) { + current_listing->paragraph(current_buffer.substr(0, 62), null_source); + current_listing->codeblock(current_buffer.substr(64), "yoscrypt", null_source); + } else + current_listing->codeblock(current_buffer, "none", null_source); + current_buffer = ""; + } } - // strip leading and trailing whitespace - std::string stripped_line = line.substr(first_pos, last_pos - first_pos +1); - bool IsDefinition = stripped_line[0] == '-'; - IsDefinition &= stripped_line[1] != ' ' && stripped_line[1] != '>'; - bool IsDedent = def_strip_count && first_pos <= def_strip_count; - bool IsIndent = first_pos == 2 || first_pos == 4; - if (cmd.compare(0, 7, "verific") == 0) - // verific.cc has strange and different formatting from the rest - IsIndent = false; - - // another usage block - bool NewUsage = stripped_line.find(cmd) == 0; - - if (IsUsage) { - if (stripped_line.compare(0, 4, "See ") == 0) { - // description refers to another function - fprintf(f, "\n %s\n", stripped_line.c_str()); - } else { - // usage should be the first line of help output - fprintf(f, "\n .. code:: yoscrypt\n\n %s\n\n ", stripped_line.c_str()); - WasDefinition = true; + // attempt auto group + if (!cmd_help.has_group()) { + string source_file = pass->location.file_name(); + bool has_source = source_file.compare("unknown") != 0; + if (pass->internal_flag) + cmd_help.group = "internal"; + else if (source_file.find("backends/") == 0 || (!has_source && name.find("read_") == 0)) + cmd_help.group = "backends"; + else if (source_file.find("frontends/") == 0 || (!has_source && name.find("write_") == 0)) + cmd_help.group = "frontends"; + else if (has_source) { + auto last_slash = source_file.find_last_of('/'); + if (last_slash != string::npos) { + auto parent_path = source_file.substr(0, last_slash); + cmd_help.group = parent_path; + } } - IsUsage = false; - } else if (IsIndent && NewUsage && (blank_count >= 2 || WasDefinition)) { - // another usage block - fprintf(f, "\n .. code:: yoscrypt\n\n %s\n\n ", stripped_line.c_str()); - WasDefinition = true; - def_strip_count = 0; - } else if (IsIndent && IsDefinition && (blank_count || WasDefinition)) { - // format definition term - fprintf(f, "\n\n .. code:: yoscrypt\n\n %s\n\n ", stripped_line.c_str()); - WasDefinition = true; - def_strip_count = first_pos; - } else { - if (IsDedent) { - fprintf(f, "\n\n ::\n"); - def_strip_count = first_pos; - } else if (WasDefinition) { - fprintf(f, "::\n"); - WasDefinition = false; - } - fprintf(f, "\n %s", line.substr(def_strip_count, std::string::npos).c_str()); + // implicit !has_source + else if (name.find("equiv") == 0) + cmd_help.group = "passes/equiv"; + else if (name.find("fsm") == 0) + cmd_help.group = "passes/fsm"; + else if (name.find("memory") == 0) + cmd_help.group = "passes/memory"; + else if (name.find("opt") == 0) + cmd_help.group = "passes/opt"; + else if (name.find("proc") == 0) + cmd_help.group = "passes/proc"; } - blank_count = 0; + if (groups.count(cmd_help.group) == 0) { + groups[cmd_help.group] = vector(); + } + groups[cmd_help.group].push_back(name); + + // write to json + json.name(name.c_str()); json.begin_object(); + json.entry("title", title); + json.name("content"); json.begin_array(); + for (auto &content : cmd_help) + json.value(content.to_json()); + json.end_array(); + json.entry("group", cmd_help.group); + json.entry("source_file", pass->location.file_name()); + json.entry("source_line", pass->location.line()); + json.entry("source_func", pass->location.function_name()); + json.entry("experimental_flag", pass->experimental_flag); + json.entry("internal_flag", pass->internal_flag); + json.end_object(); } - fputc('\n', f); + json.end_object(); - // render latex - fprintf(f, ".. only:: latex\n\n"); - fprintf(f, " ::\n\n"); - std::stringstream ss2; - ss2 << textcp; - for (std::string line; std::getline(ss2, line, '\n');) { - fprintf(f, " %s\n", line.c_str()); - } - fclose(f); - } - void write_cell_rst(Yosys::SimHelper cell, Yosys::CellType ct) - { - // open - FILE *f = fopen(stringf("docs/source/cell/%s.rst", cell.filesafe_name().c_str()).c_str(), "wt"); + json.entry("groups", groups); - // make header - string title_line; - if (cell.title.length()) - title_line = stringf("%s - %s", cell.name.c_str(), cell.title.c_str()); - else title_line = cell.name; - string underline = "\n"; - underline.insert(0, title_line.length(), '='); - fprintf(f, "%s\n", title_line.c_str()); - fprintf(f, "%s\n", underline.c_str()); - - // help text, with cell def for links - fprintf(f, ".. cell:def:: %s\n", cell.name.c_str()); - if (cell.title.length()) - fprintf(f, " :title: %s\n\n", cell.title.c_str()); - else - fprintf(f, " :title: %s\n\n", cell.name.c_str()); - std::stringstream ss; - ss << cell.desc; - for (std::string line; std::getline(ss, line, '\n');) { - fprintf(f, " %s\n", line.c_str()); - } - - // properties - fprintf(f, "\nProperties"); - fprintf(f, "\n----------\n\n"); - dict prop_dict = { - {"is_evaluable", ct.is_evaluable}, - {"is_combinatorial", ct.is_combinatorial}, - {"is_synthesizable", ct.is_synthesizable}, - }; - for (auto &it : prop_dict) { - fprintf(f, "- %s: %s\n", it.first.c_str(), it.second ? "true" : "false"); - } - - // source code - fprintf(f, "\nSimulation model (Verilog)"); - fprintf(f, "\n--------------------------\n\n"); - fprintf(f, ".. code-block:: verilog\n"); - fprintf(f, " :caption: %s\n\n", cell.source.c_str()); - std::stringstream ss2; - ss2 << cell.code; - for (std::string line; std::getline(ss2, line, '\n');) { - fprintf(f, " %s\n", line.c_str()); - } - - // footer - fprintf(f, "\n.. note::\n\n"); - fprintf(f, " This page was auto-generated from the output of\n"); - fprintf(f, " ``help %s``.\n", cell.name.c_str()); - - // close - fclose(f); + json.end_object(); + return raise_error; } bool dump_cells_json(PrettyJson &json) { // init json @@ -960,11 +1045,7 @@ struct HelpPass : public Pass { log("="); log("\n"); it.second->help(); - if (it.second->experimental_flag) { - log("\n"); - log("WARNING: THE '%s' COMMAND IS EXPERIMENTAL.\n", it.first.c_str()); - log("\n"); - } + log_warning_flags(it.second); } } else if (args[1] == "-cells") { @@ -978,44 +1059,9 @@ struct HelpPass : public Pass { log("\n"); return; } - // this option is undocumented as it is for internal use only - else if (args[1] == "-write-rst-command-reference-manual") { - for (auto &it : pass_register) { - std::ostringstream buf; - log_streams.push_back(&buf); - it.second->help(); - if (it.second->experimental_flag) { - log("\n"); - log("WARNING: THE '%s' COMMAND IS EXPERIMENTAL.\n", it.first.c_str()); - log("\n"); - } - log_streams.pop_back(); - write_cmd_rst(it.first, it.second->short_help, buf.str()); - } - } - // this option is also undocumented as it is for internal use only - else if (args[1] == "-write-rst-cells-manual") { - bool raise_error = false; - for (auto &it : yosys_celltypes.cell_types) { - auto name = it.first.str(); - if (cell_help_messages.contains(name)) { - write_cell_rst(cell_help_messages.get(name), it.second); - } else { - log("ERROR: Missing cell help for cell '%s'.\n", name.c_str()); - raise_error |= true; - } - } - if (raise_error) { - log_error("One or more cells defined in celltypes.h are missing help documentation.\n"); - } - } else if (pass_register.count(args[1])) { pass_register.at(args[1])->help(); - if (pass_register.at(args[1])->experimental_flag) { - log("\n"); - log("WARNING: THE '%s' COMMAND IS EXPERIMENTAL.\n", args[1].c_str()); - log("\n"); - } + log_warning_flags(pass_register.at(args[1])); } else if (cell_help_messages.contains(args[1])) { auto help_cell = cell_help_messages.get(args[1]); @@ -1044,7 +1090,17 @@ struct HelpPass : public Pass { log("No such command or cell type: %s\n", args[1].c_str()); return; } else if (args.size() == 3) { - if (args[1] == "-dump-cells-json") { + // this option is undocumented as it is for internal use only + if (args[1] == "-dump-cmds-json") { + PrettyJson json; + if (!json.write_to_file(args[2])) + log_error("Can't open file `%s' for writing: %s\n", args[2].c_str(), strerror(errno)); + if (dump_cmds_json(json)) { + log_abort(); + } + } + // this option is undocumented as it is for internal use only + else if (args[1] == "-dump-cells-json") { PrettyJson json; if (!json.write_to_file(args[2])) log_error("Can't open file `%s' for writing: %s\n", args[2].c_str(), strerror(errno)); @@ -1052,6 +1108,8 @@ struct HelpPass : public Pass { log_error("One or more cells defined in celltypes.h are missing help documentation.\n"); } } + else + log("Unknown help command: `%s %s'\n", args[1].c_str(), args[2].c_str()); return; } diff --git a/kernel/register.h b/kernel/register.h index f4e2127e1..534cfbc28 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -23,27 +23,62 @@ #include "kernel/yosys_common.h" #include "kernel/yosys.h" +#ifdef YOSYS_ENABLE_HELP_SOURCE + #include +# if __cpp_lib_source_location == 201907L + #include + using std::source_location; + #define HAS_SOURCE_LOCATION +# elif defined(__has_include) +# if __has_include() + #include + using std::experimental::source_location; + #define HAS_SOURCE_LOCATION +# endif +# endif +#endif + +#ifndef HAS_SOURCE_LOCATION +struct source_location { // dummy placeholder + int line() const { return 0; } + int column() const { return 0; } + const char* file_name() const { return "unknown"; } + const char* function_name() const { return "unknown"; } + static const source_location current(...) { return source_location(); } +}; +#endif + YOSYS_NAMESPACE_BEGIN struct Pass { std::string pass_name, short_help; - Pass(std::string name, std::string short_help = "** document me **"); + source_location location; + Pass(std::string name, std::string short_help = "** document me **", + source_location location = source_location::current()); // Prefer overriding 'Pass::on_shutdown()' if possible virtual ~Pass(); + // Makes calls to log() to generate help message virtual void help(); + // Uses PrettyHelp::get_current() to produce a more portable formatted help message + virtual bool formatted_help(); virtual void clear_flags(); virtual void execute(std::vector args, RTLIL::Design *design) = 0; int call_counter; int64_t runtime_ns; bool experimental_flag = false; + bool internal_flag = false; void experimental() { experimental_flag = true; } + void internal() { + internal_flag = true; + } + struct pre_post_exec_state_t { Pass *parent_pass; int64_t begin_ns; @@ -81,7 +116,8 @@ struct ScriptPass : Pass RTLIL::Design *active_design; std::string active_run_from, active_run_to; - ScriptPass(std::string name, std::string short_help = "** document me **") : Pass(name, short_help) { } + ScriptPass(std::string name, std::string short_help = "** document me **", source_location location = source_location::current()) : + Pass(name, short_help, location) { } virtual void script() = 0; @@ -99,7 +135,8 @@ struct Frontend : Pass static std::string last_here_document; std::string frontend_name; - Frontend(std::string name, std::string short_help = "** document me **"); + Frontend(std::string name, std::string short_help = "** document me **", + source_location location = source_location::current()); void run_register() override; ~Frontend() override; void execute(std::vector args, RTLIL::Design *design) override final; @@ -115,7 +152,8 @@ struct Frontend : Pass struct Backend : Pass { std::string backend_name; - Backend(std::string name, std::string short_help = "** document me **"); + Backend(std::string name, std::string short_help = "** document me **", + source_location location = source_location::current()); void run_register() override; ~Backend() override; void execute(std::vector args, RTLIL::Design *design) override final; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 189db0648..646ffcb35 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -35,7 +35,7 @@ YOSYS_NAMESPACE_BEGIN bool RTLIL::IdString::destruct_guard_ok = false; RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard; std::vector RTLIL::IdString::global_id_storage_; -dict RTLIL::IdString::global_id_index_; +std::unordered_map RTLIL::IdString::global_id_index_; #ifndef YOSYS_NO_IDS_REFCNT std::vector RTLIL::IdString::global_refcount_storage_; std::vector RTLIL::IdString::global_free_idx_list_; @@ -384,7 +384,7 @@ bool RTLIL::Const::convertible_to_int(bool is_signed) const { auto size = get_min_size(is_signed); - if (size <= 0) + if (size < 0) return false; // If it fits in 31 bits it is definitely convertible @@ -1139,6 +1139,12 @@ void RTLIL::Design::sort() it.second->sort(); } +void RTLIL::Design::sort_modules() +{ + scratchpad.sort(); + modules_.sort(sort_by_id_str()); +} + void RTLIL::Design::check() { #ifndef NDEBUG @@ -5509,6 +5515,9 @@ bool RTLIL::SigSpec::convertible_to_int(bool is_signed) const if (!is_fully_const()) return false; + if (empty()) + return true; + return RTLIL::Const(chunks_[0].data).convertible_to_int(is_signed); } @@ -5520,6 +5529,9 @@ std::optional RTLIL::SigSpec::try_as_int(bool is_signed) const if (!is_fully_const()) return std::nullopt; + if (empty()) + return 0; + return RTLIL::Const(chunks_[0].data).try_as_int(is_signed); } @@ -5529,7 +5541,10 @@ int RTLIL::SigSpec::as_int_saturating(bool is_signed) const pack(); log_assert(is_fully_const() && GetSize(chunks_) <= 1); - log_assert(!empty()); + + if (empty()) + return 0; + return RTLIL::Const(chunks_[0].data).as_int_saturating(is_signed); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 504fa0062..d53bb3129 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -23,6 +23,9 @@ #include "kernel/yosys_common.h" #include "kernel/yosys.h" +#include +#include + YOSYS_NAMESPACE_BEGIN namespace RTLIL @@ -122,7 +125,7 @@ struct RTLIL::IdString } destruct_guard; static std::vector global_id_storage_; - static dict global_id_index_; + static std::unordered_map global_id_index_; #ifndef YOSYS_NO_IDS_REFCNT static std::vector global_refcount_storage_; static std::vector global_free_idx_list_; @@ -1368,6 +1371,7 @@ struct RTLIL::Design std::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const; void sort(); + void sort_modules(); void check(); void optimize(); diff --git a/kernel/satgen.h b/kernel/satgen.h index 8a89ff9db..2c8cbda13 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -101,7 +101,9 @@ struct SatGen else vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE); } else { - std::string name = pf + (bit.wire->width == 1 ? stringf("%s", log_id(bit.wire)) : stringf("%s [%d]", log_id(bit.wire->name), bit.offset)); + std::string wire_name = RTLIL::unescape_id(bit.wire->name); + std::string name = pf + + (bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name.c_str(), bit.offset)); vec.push_back(ez->frozen_literal(name)); imported_signals[pf][bit] = vec.back(); } diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index e84676bc0..ecc8ce623 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -134,6 +134,15 @@ # define YS_COLD #endif +#ifdef __cpp_consteval +#define YOSYS_CONSTEVAL consteval +#else +// If we can't use consteval we can at least make it constexpr. +#define YOSYS_CONSTEVAL constexpr +#endif + +#define YOSYS_ABORT(s) abort() + #include "kernel/io.h" YOSYS_NAMESPACE_BEGIN diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py index 4857a9dc3..ef0862587 100644 --- a/misc/py_wrap_generator.py +++ b/misc/py_wrap_generator.py @@ -71,7 +71,7 @@ keyword_aliases = { #These can be used without any explicit conversion primitive_types = ["void", "bool", "int", "double", "size_t", "std::string", - "string", "State", "char_p"] + "string", "State", "char_p", "std::source_location", "source_location"] from enum import Enum @@ -200,7 +200,7 @@ class WType: t.cont = candidate if(t.name not in known_containers): - return None + return None return t prefix = "" @@ -447,7 +447,7 @@ class PythonDictTranslator(Translator): if types[0].attr_type != attr_types.star: text += "*" text += key_tmp_name + "->get_cpp_obj()" - + text += ", " if types[1].name not in classnames: text += val_tmp_name @@ -457,7 +457,7 @@ class PythonDictTranslator(Translator): text += val_tmp_name + "->get_cpp_obj()" text += "));\n" + prefix + "}" return text - + #Generate c++ code to translate to a boost::python::dict @classmethod def translate_cpp(c, varname, types, prefix, ref): @@ -498,7 +498,7 @@ class DictTranslator(PythonDictTranslator): #Sub_type for std::map class MapTranslator(PythonDictTranslator): insert_name = "insert" - orig_name = "std::map" + orig_name = "std::map" #Translator for std::pair. Derived from PythonDictTranslator because the #gen_type function is the same (because both have two template parameters) @@ -515,11 +515,11 @@ class TupleTranslator(PythonDictTranslator): if types[0].name.split(" ")[-1] in primitive_types: text += varname + "___tmp_0, " else: - text += varname + "___tmp_0.get_cpp_obj(), " + text += "*" + varname + "___tmp_0.get_cpp_obj(), " if types[1].name.split(" ")[-1] in primitive_types: text += varname + "___tmp_1);" else: - text += varname + "___tmp_1.get_cpp_obj());" + text += "*" + varname + "___tmp_1.get_cpp_obj());" return text #Generate c++ code to translate to a boost::python::tuple @@ -684,7 +684,7 @@ class Attribute: if self.wtype.name in known_containers: return known_containers[self.wtype.name].typename return prefix + self.wtype.name - + #Generate Translation code for the attribute def gen_translation(self): if self.wtype.name in known_containers: @@ -948,7 +948,7 @@ class WClass: text = "\n\t\tclass_<" + self.name + base_info + ">(\"" + self.name + "\"" text += body return text - + def contains_default_constr(self): for c in self.found_constrs: @@ -1137,10 +1137,18 @@ class WConstructor: str_def = str_def[0:found].strip() if len(str_def) == 0: return con - for arg in split_list(str_def, ","): + args = split_list(str_def, ",") + for i, arg in enumerate(args): parsed = Attribute.from_string(arg.strip(), containing_file, line_number) if parsed == None: return None + # Only allow std::source_location as defaulted last argument, and + # don't append so it takes default value + if parsed.wtype.name in ["std::source_location", "source_location"]: + if parsed.default_value is None or i != len(args) - 1: + debug("std::source_location not defaulted last arg of " + class_.name + " is unsupported", 2) + return None + continue con.args.append(parsed) return con @@ -1379,12 +1387,20 @@ class WFunction: str_def = str_def[:found].strip() if(len(str_def) == 0): return func - for arg in split_list(str_def, ","): + args = split_list(str_def, ",") + for i, arg in enumerate(args): if arg.strip() == "...": continue parsed = Attribute.from_string(arg.strip(), containing_file, line_number) if parsed == None: return None + # Only allow std::source_location as defaulted last argument, and + # don't append so it takes default value + if parsed.wtype.name in ["std::source_location", "source_location"]: + if parsed.default_value is None or i != len(args) - 1: + debug("std::source_location not defaulted last arg of " + func.name + " is unsupported", 2) + return None + continue func.args.append(parsed) return func @@ -1773,7 +1789,7 @@ class WMember: if self.wtype.name in classnames: text += ")" text += ";" - + if self.wtype.name in classnames: text += "\n\t\treturn *ret_;" elif self.wtype.name in known_containers: @@ -1795,12 +1811,12 @@ class WMember: text += "\n\t{" text += ret.gen_translation() text += "\n\t\tthis->get_cpp_obj()->" + self.name + " = " + ret.gen_call() + ";" - text += "\n\t}\n" + text += "\n\t}\n" return text; def gen_boost_py(self): - text = "\n\t\t\t.add_property(\"" + self.name + "\", &" + self.member_of.name + "::get_var_py_" + self.name + text = "\n\t\t\t.add_property(\"" + self.name + "\", &" + self.member_of.name + "::get_var_py_" + self.name if not self.is_const: text += ", &" + self.member_of.name + "::set_var_py_" + self.name text += ")" @@ -1926,7 +1942,7 @@ class WGlobal: if self.wtype.name in classnames: text += ")" text += ";" - + if self.wtype.name in classnames: text += "\n\t\treturn *ret_;" elif self.wtype.name in known_containers: @@ -1948,12 +1964,12 @@ class WGlobal: text += "\n\t{" text += ret.gen_translation() text += "\n\t\t" + self.namespace + "::" + self.name + " = " + ret.gen_call() + ";" - text += "\n\t}\n" + text += "\n\t}\n" return text; def gen_boost_py(self): - text = "\n\t\t\t.add_static_property(\"" + self.name + "\", &" + "YOSYS_PYTHON::get_var_py_" + self.name + text = "\n\t\t\t.add_static_property(\"" + self.name + "\", &" + "YOSYS_PYTHON::get_var_py_" + self.name if not self.is_const: text += ", &YOSYS_PYTHON::set_var_py_" + self.name text += ")" diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 4ecaea7dd..9bf615a7e 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -56,3 +56,4 @@ OBJS += passes/cmds/setenv.o OBJS += passes/cmds/abstract.o OBJS += passes/cmds/test_select.o OBJS += passes/cmds/timeest.o +OBJS += passes/cmds/linecoverage.o diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index da06acedf..08dc76dda 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -20,6 +20,16 @@ #include "kernel/yosys.h" #include "backends/rtlil/rtlil_backend.h" +#if defined(_WIN32) +# include +# define WIFEXITED(x) 1 +# define WIFSIGNALED(x) 0 +# define WIFSTOPPED(x) 0 +# define WEXITSTATUS(x) ((x) & 0xff) +# define WTERMSIG(x) SIGTERM +# define WSTOPSIG(x) 0 +#endif + USING_YOSYS_NAMESPACE using namespace RTLIL_BACKEND; PRIVATE_NAMESPACE_BEGIN @@ -50,6 +60,10 @@ struct BugpointPass : public Pass { log(" -grep \"\"\n"); log(" only consider crashes that place this string in the log file.\n"); log("\n"); + log(" -expect-return \n"); + log(" only consider crashes that return the specified value. e.g. SEGFAULT\n"); + log(" returns a value of 139.\n"); + log("\n"); log(" -fast\n"); log(" run `proc_clean; clean -purge` after each minimization step. converges\n"); log(" faster, but produces larger testcases, and may fail to produce any\n"); @@ -60,6 +74,17 @@ struct BugpointPass : public Pass { log(" finishing. produces smaller and more useful testcases, but may fail to\n"); log(" produce any testcase at all if the crash is related to dangling wires.\n"); log("\n"); + log(" -runner \"\"\n"); + log(" child process wrapping command, e.g., \"timeout 30\", or valgrind.\n"); + log("\n"); + log(" -err-grep \"\"\n"); + log(" only consider crashes that print this string on stderr. useful for\n"); + log(" errors outside of yosys.\n"); + log("\n"); + log(" -suffix \"\"\n"); + log(" add suffix to generated file names. useful when running more than one\n"); + log(" instance of bugpoint in the same directory. limited to 8 characters.\n"); + log("\n"); log("It is possible to constrain which parts of the design will be considered for\n"); log("removal. Unless one or more of the following options are specified, all parts\n"); log("will be considered.\n"); @@ -89,24 +114,39 @@ struct BugpointPass : public Pass { log(" -updates\n"); log(" try to remove process updates from syncs.\n"); log("\n"); - log(" -runner \"\"\n"); - log(" child process wrapping command, e.g., \"timeout 30\", or valgrind.\n"); + log(" -wires\n"); + log(" try to remove wires. wires with a (* bugpoint_keep *) attribute will be\n"); + log(" skipped.\n"); log("\n"); } - bool run_yosys(RTLIL::Design *design, string runner, string yosys_cmd, string yosys_arg) + int run_yosys(RTLIL::Design *design, string runner, string yosys_cmd, string yosys_arg, string suffix, bool catch_err) { design->sort(); - std::ofstream f("bugpoint-case.il"); + string bugpoint_file = "bugpoint-case"; + if (suffix.size()) + bugpoint_file += stringf(".%.8s", suffix.c_str()); + + std::ofstream f(bugpoint_file + ".il"); RTLIL_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false); f.close(); - string yosys_cmdline = stringf("%s %s -qq -L bugpoint-case.log %s bugpoint-case.il", runner.c_str(), yosys_cmd.c_str(), yosys_arg.c_str()); - return run_command(yosys_cmdline) == 0; + string yosys_cmdline = stringf("%s %s -qq -L %s.log %s %s.il", runner.c_str(), yosys_cmd.c_str(), bugpoint_file.c_str(), yosys_arg.c_str(), bugpoint_file.c_str()); + if (catch_err) yosys_cmdline += stringf(" 2>%s.err", bugpoint_file.c_str()); + auto status = run_command(yosys_cmdline); + // we're not processing lines, which means we're getting raw system() returns + if(WIFEXITED(status)) + return WEXITSTATUS(status); + else if(WIFSIGNALED(status)) + return WTERMSIG(status); + else if(WIFSTOPPED(status)) + return WSTOPSIG(status); + else + return 0; } - bool check_logfile(string grep) + bool check_logfile(string grep, string suffix, bool err=false) { if (grep.empty()) return true; @@ -114,7 +154,13 @@ struct BugpointPass : public Pass { if (grep.size() > 2 && grep.front() == '"' && grep.back() == '"') grep = grep.substr(1, grep.size() - 2); - std::ifstream f("bugpoint-case.log"); + string bugpoint_file = "bugpoint-case"; + if (suffix.size()) + bugpoint_file += stringf(".%.8s", suffix.c_str()); + bugpoint_file += err ? ".err" : ".log"; + + std::ifstream f(bugpoint_file); + while (!f.eof()) { string line; @@ -125,6 +171,11 @@ struct BugpointPass : public Pass { return false; } + bool check_logfiles(string grep, string err_grep, string suffix) + { + return check_logfile(grep, suffix) && check_logfile(err_grep, suffix, true); + } + RTLIL::Design *clean_design(RTLIL::Design *design, bool do_clean = true, bool do_delete = false) { if (!do_clean) @@ -399,7 +450,9 @@ struct BugpointPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { - string yosys_cmd = "yosys", yosys_arg, grep, runner; + string yosys_cmd = "yosys", yosys_arg, grep, err_grep, runner, suffix; + bool flag_expect_return = false, has_check = false, check_err = false; + int expect_return_value = 0; bool fast = false, clean = false; bool modules = false, ports = false, cells = false, connections = false, processes = false, assigns = false, updates = false, wires = false, has_part = false; @@ -426,9 +479,25 @@ struct BugpointPass : public Pass { continue; } if (args[argidx] == "-grep" && argidx + 1 < args.size()) { + has_check = true; grep = args[++argidx]; continue; } + if (args[argidx] == "-err-grep" && argidx + 1 < args.size()) { + has_check = true; + check_err = true; + err_grep = args[++argidx]; + continue; + } + if (args[argidx] == "-expect-return") { + flag_expect_return = true; + ++argidx; + if (argidx >= args.size()) + log_cmd_error("No expected return value specified.\n"); + + expect_return_value = atoi(args[argidx].c_str()); + continue; + } if (args[argidx] == "-fast") { fast = true; continue; @@ -485,6 +554,14 @@ struct BugpointPass : public Pass { } continue; } + if (args[argidx] == "-suffix" && argidx + 1 < args.size()) { + suffix = args[++argidx]; + if (suffix.size() && suffix.at(0) == '"') { + log_assert(suffix.back() == '"'); + suffix = suffix.substr(1, suffix.size() - 2); + } + continue; + } break; } extra_args(args, argidx, design); @@ -492,6 +569,9 @@ struct BugpointPass : public Pass { if (yosys_arg.empty()) log_cmd_error("Missing -script or -command option.\n"); + if (flag_expect_return && expect_return_value == 0 && !has_check) + log_cmd_error("Nothing to match on for -expect-return 0; change value or use -grep.\n"); + if (!has_part) { modules = true; @@ -508,10 +588,15 @@ struct BugpointPass : public Pass { log_cmd_error("This command only operates on fully selected designs!\n"); RTLIL::Design *crashing_design = clean_design(design, clean); - if (run_yosys(crashing_design, runner, yosys_cmd, yosys_arg)) + int retval = run_yosys(crashing_design, runner, yosys_cmd, yosys_arg, suffix, check_err); + if (flag_expect_return && retval != expect_return_value) + log_cmd_error("The provided script file or command and Yosys binary returned value %d instead of expected %d on this design!\n", retval, expect_return_value); + if (!flag_expect_return && retval == 0) log_cmd_error("The provided script file or command and Yosys binary do not crash on this design!\n"); - if (!check_logfile(grep)) + if (!check_logfile(grep, suffix)) log_cmd_error("The provided grep string is not found in the log file!\n"); + if (!check_logfile(err_grep, suffix, true)) + log_cmd_error("The provided grep string is not found in stderr log!\n"); int seed = 0; bool found_something = false, stage2 = false; @@ -521,21 +606,37 @@ struct BugpointPass : public Pass { { simplified = clean_design(simplified, fast, /*do_delete=*/true); - bool crashes; if (clean) { RTLIL::Design *testcase = clean_design(simplified); - crashes = !run_yosys(testcase, runner, yosys_cmd, yosys_arg); + retval = run_yosys(testcase, runner, yosys_cmd, yosys_arg, suffix, check_err); delete testcase; } else { - crashes = !run_yosys(simplified, runner, yosys_cmd, yosys_arg); + retval = run_yosys(simplified, runner, yosys_cmd, yosys_arg, suffix, check_err); } - if (crashes && check_logfile(grep)) + bool crashes = false; + if (flag_expect_return && retval == expect_return_value && check_logfiles(grep, err_grep, suffix)) + { + log("Testcase matches expected crash.\n"); + crashes = true; + } + else if (!flag_expect_return && retval == 0) + log("Testcase does not crash.\n"); + else if (!flag_expect_return && check_logfiles(grep, err_grep, suffix)) { log("Testcase crashes.\n"); + crashes = true; + } + else + // flag_expect_return && !(retval == expect_return_value && check_logfiles(grep, err_grep, suffix)) + // !flag_expect_return && !(retval == 0 && check_logfiles(grep, err_grep, suffix)) + log("Testcase does not match expected crash.\n"); + + if (crashes) + { if (crashing_design != design) delete crashing_design; crashing_design = simplified; @@ -543,7 +644,6 @@ struct BugpointPass : public Pass { } else { - log("Testcase does not crash.\n"); delete simplified; seed++; } diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 83fe781a0..8bbcb8da0 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -22,12 +22,18 @@ #include "kernel/celledges.h" #include "kernel/celltypes.h" #include "kernel/utils.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct CheckPass : public Pass { CheckPass() : Pass("check", "check for obvious problems in the design") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index e027103bb..ccda023c0 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -19,6 +19,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -70,65 +71,67 @@ static bool is_triggered_check_cell(RTLIL::Cell * cell) } struct ChformalPass : public Pass { - ChformalPass() : Pass("chformal", "change formal constraints of the design") { } - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" chformal [types] [mode] [options] [selection]\n"); - log("\n"); - log("Make changes to the formal constraints of the design. The [types] options\n"); - log("the type of constraint to operate on. If none of the following options are\n"); - log("given, the command will operate on all constraint types:\n"); - log("\n"); - log(" -assert $assert cells, representing assert(...) constraints\n"); - log(" -assume $assume cells, representing assume(...) constraints\n"); - log(" -live $live cells, representing assert(s_eventually ...)\n"); - log(" -fair $fair cells, representing assume(s_eventually ...)\n"); - log(" -cover $cover cells, representing cover() statements\n"); - log("\n"); - log(" Additionally chformal will operate on $check cells corresponding to the\n"); - log(" selected constraint types.\n"); - log("\n"); - log("Exactly one of the following modes must be specified:\n"); - log("\n"); - log(" -remove\n"); - log(" remove the cells and thus constraints from the design\n"); - log("\n"); - log(" -early\n"); - log(" bypass FFs that only delay the activation of a constraint. When inputs\n"); - log(" of the bypassed FFs do not remain stable between clock edges, this may\n"); - log(" result in unexpected behavior.\n"); - log("\n"); - log(" -delay \n"); - log(" delay activation of the constraint by clock cycles\n"); - log("\n"); - log(" -skip \n"); - log(" ignore activation of the constraint in the first clock cycles\n"); - log("\n"); - log(" -coverenable\n"); - log(" add cover statements for the enable signals of the constraints\n"); - log("\n"); + ChformalPass() : Pass("chformal", "change formal constraints of the design") {} + + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + + auto content_root = help->get_root(); + + content_root->usage("chformal [types] [mode] [options] [selection]"); + content_root->paragraph( + "Make changes to the formal constraints of the design. The [types] options " + "the type of constraint to operate on. If none of the following options are " + "given, the command will operate on all constraint types:" + ); + + content_root->option("-assert", "`$assert` cells, representing ``assert(...)`` constraints"); + content_root->option("-assume", "`$assume` cells, representing ``assume(...)`` constraints"); + content_root->option("-live", "`$live` cells, representing ``assert(s_eventually ...)``"); + content_root->option("-fair", "`$fair` cells, representing ``assume(s_eventually ...)``"); + content_root->option("-cover", "`$cover` cells, representing ``cover()`` statements"); + content_root->paragraph( + "Additionally chformal will operate on `$check` cells corresponding to the " + "selected constraint types." + ); + + content_root->paragraph("Exactly one of the following modes must be specified:"); + + content_root->option("-remove", "remove the cells and thus constraints from the design"); + content_root->option("-early", + "bypass FFs that only delay the activation of a constraint. When inputs " + "of the bypassed FFs do not remain stable between clock edges, this may " + "result in unexpected behavior." + ); + content_root->option("-delay ", "delay activation of the constraint by clock cycles"); + content_root->option("-skip ", "ignore activation of the constraint in the first clock cycles"); + auto cover_option = content_root->open_option("-coverenable"); + cover_option->paragraph( + "add cover statements for the enable signals of the constraints" + ); #ifdef YOSYS_ENABLE_VERIFIC - log(" Note: For the Verific frontend it is currently not guaranteed that a\n"); - log(" reachable SVA statement corresponds to an active enable signal.\n"); - log("\n"); + cover_option->paragraph( + "Note: For the Verific frontend it is currently not guaranteed that a " + "reachable SVA statement corresponds to an active enable signal." + ); #endif - log(" -assert2assume\n"); - log(" -assume2assert\n"); - log(" -live2fair\n"); - log(" -fair2live\n"); - log(" change the roles of cells as indicated. these options can be combined\n"); - log("\n"); - log(" -lower\n"); - log(" convert each $check cell into an $assert, $assume, $live, $fair or\n"); - log(" $cover cell. If the $check cell contains a message, also produce a\n"); - log(" $print cell.\n"); - log("\n"); + content_root->option("-assert2assume"); + content_root->option("-assert2cover"); + content_root->option("-assume2assert"); + content_root->option("-live2fair"); + content_root->option("-fair2live", "change the roles of cells as indicated. these options can be combined"); + content_root->option("-lower", + "convert each $check cell into an $assert, $assume, $live, $fair or " + "$cover cell. If the $check cell contains a message, also produce a " + "$print cell." + ); + return true; } void execute(std::vector args, RTLIL::Design *design) override { bool assert2assume = false; + bool assert2cover = false; bool assume2assert = false; bool live2fair = false; bool fair2live = false; @@ -187,6 +190,11 @@ struct ChformalPass : public Pass { mode = 'c'; continue; } + if ((mode == 0 || mode == 'c') && args[argidx] == "-assert2cover") { + assert2cover = true; + mode = 'c'; + continue; + } if ((mode == 0 || mode == 'c') && args[argidx] == "-assume2assert") { assume2assert = true; mode = 'c'; @@ -218,6 +226,10 @@ struct ChformalPass : public Pass { constr_types.insert(ID($cover)); } + if (assert2assume && assert2cover) { + log_cmd_error("Cannot use both -assert2assume and -assert2cover.\n"); + } + if (mode == 0) log_cmd_error("Mode option is missing.\n"); @@ -381,6 +393,8 @@ struct ChformalPass : public Pass { IdString flavor = formal_flavor(cell); if (assert2assume && flavor == ID($assert)) set_formal_flavor(cell, ID($assume)); + if (assert2cover && flavor == ID($assert)) + set_formal_flavor(cell, ID($cover)); else if (assume2assert && flavor == ID($assume)) set_formal_flavor(cell, ID($assert)); else if (live2fair && flavor == ID($live)) diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index 1db3e2ca0..47354f1d5 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #include #ifndef _WIN32 @@ -26,15 +27,18 @@ # include #endif -#include "kernel/register.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" - USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct CoverPass : public Pass { - CoverPass() : Pass("cover", "print code coverage counters") { } + CoverPass() : Pass("cover", "print code coverage counters") { + internal(); + } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index b6afe6f89..347c8efa4 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -22,6 +22,7 @@ #include "kernel/modtools.h" #include "kernel/sigtools.h" #include "kernel/yosys.h" +#include "kernel/log_help.h" #include USING_YOSYS_NAMESPACE @@ -952,6 +953,11 @@ struct DftTagWorker { struct DftTagPass : public Pass { DftTagPass() : Pass("dft_tag", "create tagging logic for data flow tracking") {} + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc index 5b53f50cc..933bd457f 100644 --- a/passes/cmds/edgetypes.cc +++ b/passes/cmds/edgetypes.cc @@ -19,12 +19,18 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct EdgetypePass : public Pass { EdgetypePass() : Pass("edgetypes", "list all types of edges in selection") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index 2870e062b..b10f50502 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -21,15 +21,17 @@ struct ExampleWorker struct ExampleDtPass : public Pass { - ExampleDtPass() : Pass("example_dt", "drivertools example") {} + ExampleDtPass() : Pass("example_dt", "drivertools example") { + internal(); + } - void help() override + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log("TODO: add help message\n"); log("\n"); - } + } void execute(std::vector args, RTLIL::Design *design) override diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc index e9cc34b30..486fa1c2b 100644 --- a/passes/cmds/exec.cc +++ b/passes/cmds/exec.cc @@ -17,8 +17,8 @@ * */ -#include "kernel/register.h" -#include "kernel/log.h" +#include "kernel/yosys.h" +#include "kernel/log_help.h" #include #if defined(_WIN32) @@ -38,6 +38,11 @@ PRIVATE_NAMESPACE_BEGIN struct ExecPass : public Pass { ExecPass() : Pass("exec", "execute commands in the operating system shell") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/future.cc b/passes/cmds/future.cc index b03613c9b..5dcf46bcf 100644 --- a/passes/cmds/future.cc +++ b/passes/cmds/future.cc @@ -24,6 +24,7 @@ #include "kernel/sigtools.h" #include "kernel/utils.h" #include "kernel/yosys.h" +#include "kernel/log_help.h" #include USING_YOSYS_NAMESPACE @@ -110,6 +111,11 @@ struct FutureWorker { struct FuturePass : public Pass { FuturePass() : Pass("future", "resolve future sampled value functions") {} + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index 6a7d070d7..0c321eba6 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -17,10 +17,9 @@ * */ -#include "kernel/register.h" -#include "kernel/rtlil.h" #include "kernel/utils.h" -#include "kernel/log.h" +#include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -425,6 +424,12 @@ public: struct GliftPass : public Pass { GliftPass() : Pass("glift", "create GLIFT models and optimization problems") {} + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/internal_stats.cc b/passes/cmds/internal_stats.cc index 28822f237..00456b8f9 100644 --- a/passes/cmds/internal_stats.cc +++ b/passes/cmds/internal_stats.cc @@ -18,8 +18,6 @@ */ #include -#include -#include #include "kernel/yosys.h" #include "kernel/celltypes.h" @@ -71,7 +69,10 @@ std::optional current_mem_bytes() { } struct InternalStatsPass : public Pass { - InternalStatsPass() : Pass("internal_stats", "print internal statistics") { } + InternalStatsPass() : Pass("internal_stats", "print internal statistics") { + experimental(); + internal(); + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/linecoverage.cc b/passes/cmds/linecoverage.cc new file mode 100644 index 000000000..9a88dec7f --- /dev/null +++ b/passes/cmds/linecoverage.cc @@ -0,0 +1,152 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +#include + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + + +static const std::regex src_re("(.*):(\\d+)\\.(\\d+)-(\\d+)\\.(\\d+)"); + +struct CoveragePass : public Pass { + CoveragePass() : Pass("linecoverage", "report coverage information") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" linecoverage [options] [selection]\n"); + log("\n"); + log("This command prints coverage information on the design based on the current\n"); + log("selection, where items in the selection are considered covered and items not in\n"); + log("the selection are considered uncovered. If the same source location is found\n"); + log("both on items inside and out of the selection, it is considered uncovered.\n"); + log("\n"); + log(" -lcov \n"); + log(" write coverage information in lcov format to this file\n"); + log("\n"); + } + + std::string extract_src_filename(std::string src) const + { + std::smatch m; + if (std::regex_match(src, m, src_re)) { + return m[1].str(); + }; + return ""; + } + + std::pair extract_src_lines(std::string src) const + { + std::smatch m; + if (std::regex_match(src, m, src_re)) { + return std::make_pair(stoi(m[2].str()), stoi(m[4].str())); + }; + return std::make_pair(0,0); + } + + void execute(std::vector args, RTLIL::Design *design) override + { + std::string ofile; + + log_header(design, "Executing linecoverage pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-lcov" && argidx+1 < args.size()) { + ofile = args[++argidx]; + continue; + } + break; + } + extra_args(args, argidx, design); + + std::ofstream fout; + if (!ofile.empty()) { + fout.open(ofile, std::ios::out | std::ios::trunc); + if (!fout.is_open()) + log_error("Could not open file \"%s\" with write access.\n", ofile.c_str()); + } + + std::map> uncovered_lines; + std::map> all_lines; + + for (auto module : design->modules()) + { + log_debug("Module %s:\n", log_id(module)); + for (auto wire: module->wires()) { + log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute().c_str(), log_id(wire->name)); + for (auto src: wire->get_strpool_attribute(ID::src)) { + auto filename = extract_src_filename(src); + if (filename.empty()) continue; + auto [begin, end] = extract_src_lines(src); + for (int l = begin; l <=end; l++) { + if (l == 0) continue; + all_lines[filename].insert(l); + if (!module->selected(wire)) + uncovered_lines[filename].insert(l); + } + } + } + for (auto cell: module->cells()) { + log_debug("%s\t%s\t%s\n", module->selected(cell) ? "*" : " ", cell->get_src_attribute().c_str(), log_id(cell->name)); + for (auto src: cell->get_strpool_attribute(ID::src)) { + auto filename = extract_src_filename(src); + if (filename.empty()) continue; + auto [begin, end] = extract_src_lines(src); + for (int l = begin; l <=end; l++) { + if (l == 0) continue; + all_lines[filename].insert(l); + if (!module->selected(cell)) + uncovered_lines[filename].insert(l); + } + } + } + log_debug("\n"); + } + + for (const auto& file_entry : all_lines) { + int lines_found = file_entry.second.size(); + int lines_hit = file_entry.second.size() - (uncovered_lines.count(file_entry.first) ? uncovered_lines[file_entry.first].size() : 0); + log("File %s: %d/%d lines covered\n", file_entry.first.c_str(), lines_hit, lines_found); + + if(!ofile.empty()) { + fout << "SF:" << file_entry.first << "\n"; + for (int l : file_entry.second) { + fout << "DA:" << l << ","; + if (uncovered_lines.count(file_entry.first) && uncovered_lines[file_entry.first].count(l)) + fout << "0"; + else + fout << "1"; + fout << "\n"; + } + fout << "LF:" << lines_found << "\n"; + fout << "LH:" << lines_hit << "\n"; + fout << "end_of_record\n"; + } + } + + } +} CoveragePass; + +PRIVATE_NAMESPACE_END diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc index 3b82ac48c..0238627d1 100644 --- a/passes/cmds/logcmd.cc +++ b/passes/cmds/logcmd.cc @@ -18,15 +18,19 @@ * */ -#include "kernel/register.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" +#include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct LogPass : public Pass { LogPass() : Pass("log", "print text and log files") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc index 241a8799f..276810201 100644 --- a/passes/cmds/logger.cc +++ b/passes/cmds/logger.cc @@ -17,14 +17,19 @@ * */ -#include "kernel/register.h" -#include "kernel/log.h" +#include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct LoggerPass : public Pass { LoggerPass() : Pass("logger", "set logger properties") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/ltp.cc b/passes/cmds/ltp.cc index 22bdaab44..b3134b110 100644 --- a/passes/cmds/ltp.cc +++ b/passes/cmds/ltp.cc @@ -20,6 +20,7 @@ #include "kernel/yosys.h" #include "kernel/celltypes.h" #include "kernel/sigtools.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -141,6 +142,11 @@ struct LtpWorker struct LtpPass : public Pass { LtpPass() : Pass("ltp", "print longest topological path") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 4ad7c165b..a653844b7 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #ifdef YOSYS_ENABLE_PLUGINS # include @@ -122,6 +123,11 @@ void load_plugin(std::string, std::vector) struct PluginPass : public Pass { PluginPass() : Pass("plugin", "load and list loaded plugins") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/portarcs.cc b/passes/cmds/portarcs.cc index a6ed75de3..97682efbb 100644 --- a/passes/cmds/portarcs.cc +++ b/passes/cmds/portarcs.cc @@ -22,6 +22,7 @@ #include "kernel/rtlil.h" #include "kernel/utils.h" #include "kernel/celltypes.h" +#include "kernel/log_help.h" PRIVATE_NAMESPACE_BEGIN USING_YOSYS_NAMESPACE @@ -38,6 +39,11 @@ static RTLIL::SigBit canonical_bit(RTLIL::SigBit bit) struct PortarcsPass : Pass { PortarcsPass() : Pass("portarcs", "derive port arcs for propagation delay") {} + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc index 03048422d..f78d9d3b6 100644 --- a/passes/cmds/portlist.cc +++ b/passes/cmds/portlist.cc @@ -19,12 +19,18 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct PortlistPass : public Pass { PortlistPass() : Pass("portlist", "list (top-level) ports") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc index 2a5034c13..c8b0a1d1f 100644 --- a/passes/cmds/printattrs.cc +++ b/passes/cmds/printattrs.cc @@ -18,12 +18,18 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct PrintAttrsPass : public Pass { PrintAttrsPass() : Pass("printattrs", "print attributes of selected objects") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index fe8b4a444..e0586ec7e 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -20,6 +20,7 @@ #include "kernel/register.h" #include "kernel/rtlil.h" #include "kernel/log.h" +#include "backends/verilog/verilog_backend.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -186,6 +187,26 @@ static bool rename_witness(RTLIL::Design *design, dict &ca return has_witness_signals; } +static std::string renamed_unescaped(const std::string& str) +{ + std::string new_str = ""; + + if ('0' <= str[0] && str[0] <= '9') + new_str = '_' + new_str; + + for (char c : str) { + if (VERILOG_BACKEND::char_is_verilog_escaped(c)) + new_str += '_'; + else + new_str += c; + } + + if (VERILOG_BACKEND::verilog_keywords().count(str)) + new_str += "_"; + + return new_str; +} + struct RenamePass : public Pass { RenamePass() : Pass("rename", "rename object in the design") { } void help() override @@ -252,6 +273,12 @@ struct RenamePass : public Pass { log("can be used to change the random number generator seed from the default, but it\n"); log("must be non-zero.\n"); log("\n"); + log("\n"); + log(" rename -unescape [selection]\n"); + log("\n"); + log("Rename all selected public wires and cells that have to be escaped in Verilog.\n"); + log("Replaces characters with underscores or adds additional underscores and numbers.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { @@ -265,6 +292,7 @@ struct RenamePass : public Pass { bool flag_top = false; bool flag_output = false; bool flag_scramble_name = false; + bool flag_unescape = false; bool got_mode = false; unsigned int seed = 1; @@ -312,6 +340,11 @@ struct RenamePass : public Pass { got_mode = true; continue; } + if (arg == "-unescape" && !got_mode) { + flag_unescape = true; + got_mode = true; + continue; + } if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) { int pos = args[++argidx].find('%'); pattern_prefix = args[argidx].substr(0, pos); @@ -491,6 +524,48 @@ struct RenamePass : public Pass { module->rename(it.first, it.second); } } + else if (flag_unescape) + { + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + { + dict new_wire_names; + dict new_cell_names; + + for (auto wire : module->selected_wires()) { + auto name = wire->name.str(); + if (name[0] != '\\') + continue; + name = name.substr(1); + if (!VERILOG_BACKEND::id_is_verilog_escaped(name)) + continue; + new_wire_names[wire] = module->uniquify("\\" + renamed_unescaped(name)); + auto new_name = new_wire_names[wire].str().substr(1); + if (VERILOG_BACKEND::id_is_verilog_escaped(new_name)) + log_error("Failed to rename wire %s -> %s\n", name.c_str(), new_name.c_str()); + } + + for (auto cell : module->selected_cells()) { + auto name = cell->name.str(); + if (name[0] != '\\') + continue; + name = name.substr(1); + if (!VERILOG_BACKEND::id_is_verilog_escaped(name)) + continue; + new_cell_names[cell] = module->uniquify("\\" + renamed_unescaped(name)); + auto new_name = new_cell_names[cell].str().substr(1); + if (VERILOG_BACKEND::id_is_verilog_escaped(new_name)) + log_error("Failed to rename cell %s -> %s\n", name.c_str(), new_name.c_str()); + } + + for (auto &it : new_wire_names) + module->rename(it.first, it.second); + + for (auto &it : new_cell_names) + module->rename(it.first, it.second); + } + } else { if (argidx+2 != args.size()) diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 0f988e57a..e55e63828 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -21,12 +21,10 @@ // Tarjan, R. E. (1972), "Depth-first search and linear graph algorithms", SIAM Journal on Computing 1 (2): 146-160, doi:10.1137/0201010 // http://en.wikipedia.org/wiki/Tarjan's_strongly_connected_components_algorithm -#include "kernel/register.h" +#include "kernel/yosys.h" #include "kernel/celltypes.h" #include "kernel/sigtools.h" -#include "kernel/log.h" -#include -#include +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -252,6 +250,11 @@ struct SccWorker struct SccPass : public Pass { SccPass() : Pass("scc", "detect strongly connected components (logic loops)") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc index aecc4c17d..4a63f2f60 100644 --- a/passes/cmds/scratchpad.cc +++ b/passes/cmds/scratchpad.cc @@ -18,15 +18,19 @@ * */ -#include "kernel/register.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" +#include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct ScratchpadPass : public Pass { ScratchpadPass() : Pass("scratchpad", "get/set values in the scratchpad") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 1d75091af..901f923f8 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -20,8 +20,7 @@ #include "kernel/yosys.h" #include "kernel/celltypes.h" #include "kernel/sigtools.h" -#include -#include +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -1085,6 +1084,11 @@ PRIVATE_NAMESPACE_BEGIN struct SelectPass : public Pass { SelectPass() : Pass("select", "modify and view the list of selected objects") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -1664,6 +1668,11 @@ struct SelectPass : public Pass { struct CdPass : public Pass { CdPass() : Pass("cd", "a shortcut for 'select -module '") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -1776,6 +1785,11 @@ static void log_matches(const char *title, Module *module, const T &list) struct LsPass : public Pass { LsPass() : Pass("ls", "list modules or objects in modules") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/setenv.cc b/passes/cmds/setenv.cc index 27f2eea28..850d7c961 100644 --- a/passes/cmds/setenv.cc +++ b/passes/cmds/setenv.cc @@ -17,15 +17,18 @@ * */ -#include "kernel/register.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" -#include +#include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct SetenvPass : public Pass { SetenvPass() : Pass("setenv", "set an environment variable") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 8a1bd58c4..4eb6569e6 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -17,10 +17,9 @@ * */ -#include "kernel/register.h" +#include "kernel/yosys.h" #include "kernel/celltypes.h" -#include "kernel/log.h" -#include +#include "kernel/log_help.h" #ifndef _WIN32 # include @@ -658,6 +657,11 @@ struct ShowWorker struct ShowPass : public Pass { ShowPass() : Pass("show", "generate schematics using graphviz") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/sta.cc b/passes/cmds/sta.cc index 4ad0e96be..5dfac1575 100644 --- a/passes/cmds/sta.cc +++ b/passes/cmds/sta.cc @@ -21,6 +21,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" #include "kernel/timinginfo.h" +#include "kernel/log_help.h" #include USING_YOSYS_NAMESPACE @@ -275,6 +276,11 @@ struct StaWorker struct StaPass : public Pass { StaPass() : Pass("sta", "perform static timing analysis") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 6b93621f1..af7023bdd 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -25,6 +25,7 @@ #include "kernel/cost.h" #include "kernel/gzip.h" #include "libs/json11/json11.hpp" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -367,6 +368,11 @@ void read_liberty_cellarea(dict &cell_area, string libert struct StatPass : public Pass { StatPass() : Pass("stat", "print some statistics") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index 853f1bad3..fbd42e311 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -18,15 +18,19 @@ * */ -#include "kernel/register.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" +#include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct TeePass : public Pass { TeePass() : Pass("tee", "redirect command output to file") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/torder.cc b/passes/cmds/torder.cc index 1620c0bca..537b6793d 100644 --- a/passes/cmds/torder.cc +++ b/passes/cmds/torder.cc @@ -21,12 +21,18 @@ #include "kernel/celltypes.h" #include "kernel/sigtools.h" #include "kernel/utils.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct TorderPass : public Pass { TorderPass() : Pass("torder", "print cells in topological order") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index 400542776..39ed8e60e 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -19,6 +19,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -60,6 +61,11 @@ struct TraceMonitor : public RTLIL::Monitor struct TracePass : public Pass { TracePass() : Pass("trace", "redirect command output to file") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -96,6 +102,11 @@ struct TracePass : public Pass { struct DebugPass : public Pass { DebugPass() : Pass("debug", "run command with debug log messages enabled") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/viz.cc b/passes/cmds/viz.cc index 131e799ab..4c73b4d71 100644 --- a/passes/cmds/viz.cc +++ b/passes/cmds/viz.cc @@ -19,6 +19,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" +#include "kernel/log_help.h" #ifndef _WIN32 # include @@ -817,6 +818,11 @@ struct VizWorker struct VizPass : public Pass { VizPass() : Pass("viz", "visualize data flow graph") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc index ea9b3f556..a22fdaf2a 100644 --- a/passes/cmds/write_file.cc +++ b/passes/cmds/write_file.cc @@ -19,12 +19,18 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct WriteFileFrontend : public Frontend { WriteFileFrontend() : Frontend("=write_file", "write a text to a file") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/status"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc index dc5befc27..d2d0c4d8e 100644 --- a/passes/cmds/xprop.cc +++ b/passes/cmds/xprop.cc @@ -24,6 +24,7 @@ #include "kernel/sigtools.h" #include "kernel/utils.h" #include "kernel/yosys.h" +#include "kernel/log_help.h" #include USING_YOSYS_NAMESPACE @@ -1100,6 +1101,11 @@ struct XpropWorker struct XpropPass : public Pass { XpropPass() : Pass("xprop", "formal x propagation") {} + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/hierarchy/Makefile.inc b/passes/hierarchy/Makefile.inc index 3cd1b6180..ff1a2fcc5 100644 --- a/passes/hierarchy/Makefile.inc +++ b/passes/hierarchy/Makefile.inc @@ -1,4 +1,5 @@ +OBJS += passes/hierarchy/flatten.o OBJS += passes/hierarchy/hierarchy.o OBJS += passes/hierarchy/uniquify.o OBJS += passes/hierarchy/submod.o diff --git a/passes/techmap/flatten.cc b/passes/hierarchy/flatten.cc similarity index 94% rename from passes/techmap/flatten.cc rename to passes/hierarchy/flatten.cc index 6363b3432..299b18006 100644 --- a/passes/techmap/flatten.cc +++ b/passes/hierarchy/flatten.cc @@ -24,20 +24,36 @@ #include #include #include +#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -IdString concat_name(RTLIL::Cell *cell, IdString object_name, const std::string &separator = ".") +template +[[nodiscard]] std::string concat_views(const Args&... views) { + static_assert((std::is_convertible_v && ...), + "All arguments must be convertible to std::string_view."); + const std::size_t total_size = (std::string_view(views).size() + ... + 0); + + std::string result; + result.reserve(total_size); + + (result.append(views), ...); + return result; +} + +IdString concat_name(RTLIL::Cell *cell, IdString const &object_name, const std::string &separator = ".") { - if (object_name[0] == '\\') - return stringf("%s%s%s", cell->name.c_str(), separator.c_str(), object_name.c_str() + 1); - else { - std::string object_name_str = object_name.str(); - if (object_name_str.substr(0, 8) == "$flatten") - object_name_str.erase(0, 8); - return stringf("$flatten%s%s%s", cell->name.c_str(), separator.c_str(), object_name_str.c_str()); + std::string_view object_name_view(object_name.c_str()); + if (object_name_view[0] == '\\'){ + return concat_views(cell->name.c_str(), separator, object_name_view.substr(1)); } + + constexpr std::string_view prefix = "$flatten"; + if (object_name_view.substr(0, prefix.size()) == prefix){ + object_name_view.remove_prefix(prefix.size()); + } + return concat_views(prefix, cell->name.c_str(), separator, object_name_view); } template diff --git a/passes/memory/memlib.md b/passes/memory/memlib.md index 855aa1345..f3c0dd937 100644 --- a/passes/memory/memlib.md +++ b/passes/memory/memlib.md @@ -148,7 +148,7 @@ The rules for this property are as follows: - for every available width, the width needs to be a multiple of the byte size, or the byte size needs to be larger than the width -- if the byte size is larger than the width, the byte enable signel is assumed +- if the byte size is larger than the width, the byte enable signal is assumed to be one bit wide and cover the whole port - otherwise, the byte enable signal has one bit for every `byte` bits of the data port @@ -176,7 +176,7 @@ Eg. for the following properties: The cost of a given cell will be assumed to be `(8 - 7) + 7 * (used_bits / 14)`. If `widthscale` is used, The pass will attach a `BITS_USED` parameter to mapped -calls, with a bitmask of which data bits of the memory are actually in use. +cells, with a bitmask of which data bits of the memory are actually in use. The parameter width will be the widest width in the `widths` property, and the bit correspondence is defined accordingly. @@ -193,7 +193,7 @@ one of the following values: - `zero`: the memory contents are zero, memories can be mapped to this cell iff their initialization value is entirely zero or undef - `any`: the memory contents can be arbitrarily selected, and the initialization - will be passes as the `INIT` parameter to the mapped cell + will be passed as the `INIT` parameter to the mapped cell - `no_undef`: like `any`, but only 0 and 1 bit values are supported (the pass will convert any x bits to 0) @@ -234,7 +234,7 @@ Ports come in 5 kinds: - `ar`: asynchronous read port - `sr`: synchronous read port - `sw`: synchronous write port -- `arsw`: simultanous synchronous write + asynchronous read with common address (commonly found in LUT RAMs) +- `arsw`: simultaneous synchronous write + asynchronous read with common address (commonly found in LUT RAMs) - `srsw`: synchronous write + synchronous read with common address The port properties available are: @@ -419,7 +419,7 @@ If not provided, `none` is assumed for all three properties. The `wrprio` property is only allowed on write ports and defines a priority relationship between port — when `wrprio "B";` is used in definition of port `"A"`, and both ports -simultanously write to the same memory cell, the value written by port `"A"` will have +simultaneously write to the same memory cell, the value written by port `"A"` will have precedence. This property is optional, and can be used multiple times as necessary. If no relationship @@ -493,7 +493,7 @@ will disallow combining the RAM option `ABC = 2` with port option `DEF = "GHI"`. ## Ifdefs -To allow reusing a library for multiple FPGA families with slighly differing +To allow reusing a library for multiple FPGA families with slightly differing capabilities, `ifdef` (and `ifndef`) blocks are provided: ifdef IS_FANCY_FPGA_WITH_CONFIGURABLE_ASYNC_RESET { diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index 08d8191c7..426d9a79a 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -11,6 +11,7 @@ OBJS += passes/opt/opt_dff.o OBJS += passes/opt/opt_share.o OBJS += passes/opt/opt_clean.o OBJS += passes/opt/opt_expr.o +OBJS += passes/opt/opt_hier.o ifneq ($(SMALL),1) OBJS += passes/opt/share.o diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index dc88563c2..146c21cce 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -46,6 +46,7 @@ struct OptPass : public Pass { log(" opt_merge [-share_all]\n"); log(" opt_share (-full only)\n"); log(" opt_dff [-nodffe] [-nosdff] [-keepdc] [-sat] (except when called with -noff)\n"); + log(" opt_hier (-hier only)\n"); log(" opt_clean [-purge]\n"); log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]\n"); log(" while \n"); @@ -56,6 +57,7 @@ struct OptPass : public Pass { log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]\n"); log(" opt_merge [-share_all]\n"); log(" opt_dff [-nodffe] [-nosdff] [-keepdc] [-sat] (except when called with -noff)\n"); + log(" opt_hier (-hier only)\n"); log(" opt_clean [-purge]\n"); log(" while \n"); log("\n"); @@ -74,6 +76,7 @@ struct OptPass : public Pass { bool opt_share = false; bool fast_mode = false; bool noff_mode = false; + bool hier_mode = false; log_header(design, "Executing OPT pass (performing simple optimizations).\n"); log_push(); @@ -141,6 +144,10 @@ struct OptPass : public Pass { noff_mode = true; continue; } + if (args[argidx] == "-hier") { + hier_mode = true; + continue; + } break; } extra_args(args, argidx, design); @@ -155,6 +162,8 @@ struct OptPass : public Pass { Pass::call(design, "opt_dff" + opt_dff_args); if (design->scratchpad_get_bool("opt.did_something") == false) break; + if (hier_mode) + Pass::call(design, "opt_hier"); Pass::call(design, "opt_clean" + opt_clean_args); log_header(design, "Rerunning OPT passes. (Removed registers in this run.)\n"); } @@ -173,6 +182,8 @@ struct OptPass : public Pass { Pass::call(design, "opt_share"); if (!noff_mode) Pass::call(design, "opt_dff" + opt_dff_args); + if (hier_mode) + Pass::call(design, "opt_hier"); Pass::call(design, "opt_clean" + opt_clean_args); Pass::call(design, "opt_expr" + opt_expr_args); if (design->scratchpad_get_bool("opt.did_something") == false) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 4ed4b0cb6..210c4828f 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -170,9 +170,62 @@ struct OptDffWorker return ret; } - void simplify_patterns(patterns_t&) + void simplify_patterns(patterns_t& patterns) { - // TBD + auto new_patterns = patterns; + auto find_comp = [](const auto& left, const auto& right) -> std::optional { + std::optional ret; + for (const auto &pt: left) + if (right.count(pt.first) == 0) + return {}; + else if (right.at(pt.first) == pt.second) + continue; + else + if (ret) + return {}; + else + ret = pt.first; + return ret; + }; + + // remove complimentary patterns + bool optimized; + do { + optimized = false; + for (auto i = patterns.begin(); i != patterns.end(); i++) { + for (auto j = std::next(i, 1); j != patterns.end(); j++) { + const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; + auto right = (GetSize(*i) < GetSize(*j)) ? *j : *i; + + const auto complimentary_var = find_comp(left, right); + + if (complimentary_var) { + new_patterns.erase(right); + right.erase(complimentary_var.value()); + new_patterns.insert(right); + optimized = true; + } + } + } + patterns = new_patterns; + } while(optimized); + + // remove redundant patterns + for (auto i = patterns.begin(); i != patterns.end(); ++i) { + for (auto j = std::next(i, 1); j != patterns.end(); ++j) { + const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i; + const auto& right = (GetSize(*i) < GetSize(*j)) ? *j : *i; + + bool redundant = true; + + for (const auto& pt : left) + if (right.count(pt.first) == 0 || right.at(pt.first) != pt.second) + redundant = false; + if (redundant) + new_patterns.erase(right); + } + } + patterns = std::move(new_patterns); } ctrl_t make_patterns_logic(const patterns_t &patterns, const ctrls_t &ctrls, bool make_gates) diff --git a/passes/opt/opt_hier.cc b/passes/opt/opt_hier.cc new file mode 100644 index 000000000..a8df78dc1 --- /dev/null +++ b/passes/opt/opt_hier.cc @@ -0,0 +1,470 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) Martin Povišer + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +// Used to propagate information out of a module +struct ModuleIndex { + Module *module; + SigMap sigmap; + SigPool used; + dict constant_outputs; + std::vector tie_together_outputs; + + ModuleIndex(Module *module) + : module(module), sigmap(module) + { + if (module->get_blackbox_attribute()) { + for (auto wire : module->wires()) { + for (auto bit : SigSpec(wire)) + used.add(sigmap(bit)); + } + return; + } + + auto count_usage = [&](const SigSpec &signal) { + for (auto bit : signal) + used.add(sigmap(bit)); + }; + for (auto wire : module->wires()) { + if (wire->port_output) { + SigSpec wire1 = wire; + count_usage(wire1); + } + } + for (auto [_, process] : module->processes) + process->rewrite_sigspecs(count_usage); + for (auto cell : module->cells()) { + bool known = cell->known(); + for (auto &conn : cell->connections()) { + if (!known || cell->input(conn.first)) + count_usage(conn.second); + } + } + + + dict classes; + for (auto &pair : module->connections_) { + for (int i = 0; i < pair.first.size(); i++) { + if (pair.first[i].wire + && pair.first[i].wire->port_output + && !pair.first[i].wire->port_input) { + if (!pair.second[i].wire) { + constant_outputs[pair.first[i]] = pair.second[i]; + } else { + classes[pair.second[i]].append(pair.first[i]); + } + } + } + } + + for (auto [key, new_class] : classes) { + if (new_class.size() > 1) { + new_class.sort_and_unify(); + tie_together_outputs.push_back(new_class); + } + } + } + + bool apply_changes(ModuleIndex &parent, Cell *instantiation) { + log_assert(instantiation->module == parent.module); + + if (module->get_blackbox_attribute()) { + // no propagating out of blackboxes + return false; + } + + bool changed = false; + for (auto &[port_name, value] : instantiation->connections_) { + Wire *port = module->wire(port_name); + if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) { + log_error("Port %s connected on instance %s not found in module %s" + " or width is not matching\n", + log_id(port_name), log_id(instantiation), log_id(module)); + } + + if (port->port_input && port->port_output) { + // ignore bidirectional: hard to come up with sound handling + continue; + } + + int nunused = 0, nconstants = 0; + // disconnect unused inputs + if (port->port_input) { + for (int i = 0; i < port->width; i++) { + if (value[i].is_wire() && !used.check(sigmap(SigBit(port, i)))) { + value[i] = RTLIL::Sx; + nunused++; + } + } + } + + // propagate constants + if (port->port_output) { + SigSpec port_new_const; + + for (int i = 0; i < port->width; i++) { + SigBit port_bit(port, i); + if (value[i].is_wire() && constant_outputs.count(port_bit) && parent.used.check(value[i])) { + port_new_const.append(port_bit); + nconstants++; + } + } + + for (auto chunk : port_new_const.chunks()) { + RTLIL::SigSpec rhs = chunk; + rhs.replace(constant_outputs); + log_assert(rhs.is_fully_const()); + parent.module->connect(value.extract(chunk.offset, chunk.width), rhs); + SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("const_output"), chunk.width); + for (int i = 0; i < chunk.width; i++) + value[chunk.offset + i] = dummy[i]; + } + } + + if (nunused > 0) { + log("Disconnected %d input bits of instance '%s' of '%s' in '%s'\n", + nunused, log_id(instantiation), log_id(instantiation->type), log_id(parent.module)); + changed = true; + } + if (nconstants > 0) { + log("Substituting constant for %d output bits of instance '%s' of '%s' in '%s'\n", + nconstants, log_id(instantiation), log_id(instantiation->type), log_id(parent.module)); + changed = true; + } + } + + // propagate tie-togethers + int ntie_togethers = 0; + SigSpec severed_port_bits; + for (auto class_ : tie_together_outputs) { + // filtered class represented by bits on the two sides of boundary + SigSpec new_tie; + + for (auto port_bit : class_) { + if (instantiation->connections_.count(port_bit.wire->name)) { + SigBit bit = instantiation->connections_.at(port_bit.wire->name)[port_bit.offset]; + if (parent.used.check(bit)) { + if (!new_tie.empty()) { + severed_port_bits.append(port_bit); + ntie_togethers++; + } + new_tie.append(bit); + } + } + } + + if (new_tie.size() > 1) + parent.module->connect(new_tie.extract_end(1), SigSpec(new_tie[0]).repeat(new_tie.size() - 1)); + } + + severed_port_bits.sort_and_unify(); + for (auto chunk : severed_port_bits.chunks()) { + SigSpec &value = instantiation->connections_.at(chunk.wire->name); + SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("tie_together"), chunk.width); + for (int i = 0; i < chunk.width; i++) + value[chunk.offset + i] = dummy[i]; + } + + if (ntie_togethers > 0) { + log("Replacing %d output bits with tie-togethers on instance '%s' of '%s' in '%s'\n", + ntie_togethers, log_id(instantiation), log_id(instantiation->type), log_id(parent.module)); + changed = true; + } + + return changed; + } +}; + +// Used to propagate information into a module +struct UsageData { + Module *module; + SigPool used_outputs; + // Values are constant nets. We're not using `dict` + // since we want to use this with `SigSpec::replace()` + dict constant_inputs; + std::vector tie_together_inputs; + + SigSpec all_inputs; + SigSpec all_outputs; + + UsageData(Module *module) + : module(module) + { + SigSpec all_inputs; + + for (auto port_name : module->ports) { + Wire *port = module->wire(port_name); + log_assert(port); + + if (port->port_input && port->port_output) { + // ignore bidirectional: hard to come up with sound handling + continue; + } + + if (port->port_input) { + for (int i = 0; i < port->width; i++) { + constant_inputs[SigBit(port, i)] = RTLIL::Sx; + } + all_inputs.append(port); + } else { + all_outputs.append(port); + } + } + + tie_together_inputs.push_back(all_inputs); + } + + void refine_used_outputs(Wire *port, SigSpec connection, ModuleIndex &index) { + for (int i = 0; i < port->width; i++) { + if (connection[i].is_wire() && index.used.check(index.sigmap(connection[i]))) { + used_outputs.add(SigBit(port, i)); + } + } + } + + void refine_input_constants(Wire *port, SigSpec connection) { + for (int i = 0; i < port->width; i++) { + SigBit port_bit(port, i); + // is connnected constant incompatible with candidate constant? + if (connection[i] != RTLIL::Sx + && constant_inputs.count(port_bit) + && constant_inputs.at(port_bit) != connection[i]) { + // we can go Sx -> S1/S0, otherwise erase the candidate constant + if (constant_inputs.at(port_bit) == RTLIL::Sx && !connection[i].is_wire()) { + constant_inputs[port_bit] = connection[i]; + } else { + constant_inputs.erase(port_bit); + } + } + } + } + + void refine_tie_togethers(const dict &inputs) { + std::vector new_tie_togethers; + + for (auto &class_ : tie_together_inputs) { + dict new_classes; + + for (auto bit : class_) { + SigBit connected_bit = inputs.count(bit) ? inputs.at(bit) : RTLIL::Sx; + new_classes[connected_bit].append(bit); + } + + for (auto [key, new_class] : new_classes) { + if (new_class.size() > 1) + new_tie_togethers.push_back(new_class); + } + } + + new_tie_togethers.swap(tie_together_inputs); + } + + // inspect the given instantiation and refine usage data accordingly + void refine(Cell *instance, ModuleIndex &index) { + dict inputs; + + for (auto &[port_name, value] : instance->connections_) { + Wire *port = module->wire(port_name); + if (!port || (!port->port_input && !port->port_output) || port->width != value.size()) { + log_error("Port %s connected on instance %s not found in module %s" + " or width is not matching\n", + log_id(port_name), log_id(instance), log_id(module)); + } + + if (port->port_input && port->port_output) { + // ignore bidirectional: hard to come up with sound handling + continue; + } + + if (port->port_output) { + refine_used_outputs(port, value, index); + } else { + refine_input_constants(port, value); + for (int i = 0; i < port->width; i++) + inputs[SigBit(port, i)] = value[i]; + } + } + + refine_tie_togethers(inputs); + } + + bool apply_changes() { + bool did_something = false; + + if (module->get_blackbox_attribute()) { + // no propagating into blackboxes + return false; + } + + // Disconnect unused outputs + for (auto &pair : module->connections_) { + for (int i = 0; i < pair.first.size(); i++) { + // If an output is constant there's no benefit to disconnecting + // so consider it "used" + if (pair.first[i].wire + && pair.first[i].wire->port_output + && !pair.second[i].wire) + used_outputs.add(pair.first[i]); + } + } + + SigSpec disconnect_outputs; + for (auto bit : all_outputs) { + if (!used_outputs.check(bit)) + disconnect_outputs.append(bit); + } + + dict replacement_map; + for (auto chunk : disconnect_outputs.chunks()) { + Wire *repl_wire = module->addWire(module->uniquify(std::string("$") + chunk.wire->name.str()), chunk.size()); + for (int i = 0; i < repl_wire->width; i++) + replacement_map[SigSpec(chunk)[i]] = SigBit(repl_wire, i); + } + auto disconnect_rewrite = [&](SigSpec &signal) { + signal.replace(replacement_map); + }; + module->rewrite_sigspecs(disconnect_rewrite); + for (auto chunk : disconnect_outputs.chunks()) { + log("Disconnected unused output terminal '%s' in module '%s'\n", log_signal(chunk), log_id(module)); + did_something = true; + module->connect(chunk, SigSpec(RTLIL::Sx, chunk.size())); + } + + // Connect constant inputs + SigPool applied_constants; + auto constant_rewrite = [&](SigSpec &signal) { + for (auto bit : signal) { + if (constant_inputs.count(bit)) + applied_constants.add(bit); + } + signal.replace(constant_inputs); + }; + module->rewrite_sigspecs(constant_rewrite); + SigSpec applied_constants2 = applied_constants.export_all(); + applied_constants2.sort_and_unify(); + for (auto chunk : applied_constants2.chunks()) { + SigSpec const_ = chunk; + const_.replace(constant_inputs); + log("Substituting constant %s for input terminal '%s' in module '%s'\n", + log_signal(const_), log_signal(chunk), log_id(module)); + } + + // Propagate tied-together inputs + dict ties; + for (auto group : tie_together_inputs) { + for (int i = 1; i < group.size(); i++) + ties[group[i]] = group[0]; + } + SigPool applied_ties; + auto ties_rewrite = [&](SigSpec &signal) { + for (auto bit : signal) { + if (ties.count(bit)) { + applied_ties.add(bit); + } + } + signal.replace(ties); + }; + module->rewrite_sigspecs(ties_rewrite); + if (applied_ties.size()) { + log("Replacing %zu input terminal bits with tie-togethers in module '%s'\n", + applied_ties.size(), log_id(module)); + } + return did_something; + } +}; + +struct OptHierPass : Pass { + OptHierPass() : Pass("opt_hier", "perform cross-boundary optimization") {} + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" opt_hier [selection]\n"); + log("\n"); + log("This pass considers the design hierarchy and propagates unused signals, constant\n"); + log("signals, and tied-together signals across module boundaries to facilitate\n"); + log("optimization. Only the selected modules are affected.\n"); + log("\n"); + log("Note this pass changes port semantics on modules which are not the top.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *d) override + { + log_header(d, "Executing OPT_HIER pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + break; + } + extra_args(args, argidx, d); + + if (!d->top_module()) + log_cmd_error("Top module needs to be selected for opt_hier\n"); + + dict indices; + for (auto module : d->modules()) { + log_debug("Building index for %s\n", log_id(module)); + indices.emplace(module->name, ModuleIndex(module)); + } + + dict usage_datas; + for (auto module : d->selected_modules(RTLIL::SELECT_WHOLE_ONLY, RTLIL::SB_UNBOXED_CMDERR)) { + if (module->get_bool_attribute(ID::top)) + continue; + + log_debug("Starting usage data for %s\n", log_id(module)); + usage_datas.emplace(module->name, UsageData(module)); + } + + for (auto module : d->modules()) { + for (auto cell : module->cells()) { + if (usage_datas.count(cell->type)) { + log_debug("Account for instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module)); + usage_datas.at(cell->type).refine(cell, indices.at(module->name)); + } + } + } + + bool did_something = false; + for (auto module : d->selected_modules(RTLIL::SELECT_WHOLE_ONLY, RTLIL::SB_UNBOXED_CMDERR)) { + if (usage_datas.count(module->name)) { + log_debug("Applying usage data changes to %s\n", log_id(module)); + did_something |= usage_datas.at(module->name).apply_changes(); + } + + ModuleIndex &parent_index = indices.at(module->name); + for (auto cell : module->cells()) { + if (indices.count(cell->type)) { + log_debug("Applying changes to instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module)); + did_something |= indices.at(cell->type).apply_changes(parent_index, cell); + } + } + } + if (did_something) + d->scratchpad_set_bool("opt.did_something", true); + } +} OptHierPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc index 9fa9f5c2d..0ac391790 100644 --- a/passes/opt/rmports.cc +++ b/passes/opt/rmports.cc @@ -17,17 +17,20 @@ * */ -#include "kernel/register.h" #include "kernel/sigtools.h" -#include "kernel/log.h" -#include -#include +#include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct RmportsPassPass : public Pass { RmportsPassPass() : Pass("rmports", "remove module ports with no connections") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("techlibs/greenpak4"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index fc41848f7..892500850 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -117,7 +117,9 @@ void opt_eqpmux(test_pmgen_pm &pm) } struct TestPmgenPass : public Pass { - TestPmgenPass() : Pass("test_pmgen", "test pass for pmgen") { } + TestPmgenPass() : Pass("test_pmgen", "test pass for pmgen") { + internal(); + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index 991977ab9..7b3357f82 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #include "kernel/sigtools.h" #include "kernel/utils.h" @@ -182,6 +183,11 @@ struct AssertpmuxWorker struct AssertpmuxPass : public Pass { AssertpmuxPass() : Pass("assertpmux", "adds asserts for parallel muxes") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index 93c7e96c8..e86a78d81 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #include "kernel/sigtools.h" #include "kernel/ffinit.h" #include "kernel/ff.h" @@ -27,6 +28,11 @@ PRIVATE_NAMESPACE_BEGIN struct Async2syncPass : public Pass { Async2syncPass() : Pass("async2sync", "convert async FF inputs to sync circuits") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 348bab727..6b94cbe19 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #include "kernel/sigtools.h" #include "kernel/ffinit.h" #include "kernel/ff.h" @@ -33,6 +34,11 @@ struct SampledSig { struct Clk2fflogicPass : public Pass { Clk2fflogicPass() : Pass("clk2fflogic", "convert clocked FFs to generic $ff cells") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index dcd399a57..485e44fd6 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #include "kernel/sigtools.h" USING_YOSYS_NAMESPACE @@ -25,6 +26,11 @@ PRIVATE_NAMESPACE_BEGIN struct CutpointPass : public Pass { CutpointPass() : Pass("cutpoint", "adds formal cut points to the design") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 9afe00d5c..1e975db0f 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -17,11 +17,10 @@ * */ -#include "kernel/register.h" +#include "kernel/yosys.h" #include "kernel/celltypes.h" #include "kernel/sigtools.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -217,6 +216,11 @@ RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width struct ExposePass : public Pass { ExposePass() : Pass("expose", "convert internal signals to module ports") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/cmds"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index 220cf5c52..575b2f40d 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" @@ -237,6 +238,11 @@ struct FmcombineWorker struct FmcombinePass : public Pass { FmcombinePass() : Pass("fmcombine", "combine two instances of a cell into one") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc index 5f4ec0068..547082164 100644 --- a/passes/sat/fminit.cc +++ b/passes/sat/fminit.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #include "kernel/sigtools.h" USING_YOSYS_NAMESPACE @@ -25,6 +26,11 @@ PRIVATE_NAMESPACE_BEGIN struct FminitPass : public Pass { FminitPass() : Pass("fminit", "set init values/sequences for formal") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc index 1d87fcc3b..286bf2976 100644 --- a/passes/sat/formalff.cc +++ b/passes/sat/formalff.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #include "kernel/sigtools.h" #include "kernel/ffinit.h" #include "kernel/ff.h" @@ -486,6 +487,11 @@ void HierarchyWorker::propagate() struct FormalFfPass : public Pass { FormalFfPass() : Pass("formalff", "prepare FFs for formal") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 52e80f667..6063c5ab9 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -17,17 +17,12 @@ * */ -#include "kernel/register.h" #include "kernel/celltypes.h" #include "kernel/consteval.h" #include "kernel/sigtools.h" -#include "kernel/log.h" #include "kernel/satgen.h" -#include -#include -#include -#include -#include +#include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -761,6 +756,11 @@ struct FreduceWorker struct FreducePass : public Pass { FreducePass() : Pass("freduce", "perform functional reduction") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 8f27c4c6f..9bcf25547 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -17,9 +17,8 @@ * */ -#include "kernel/register.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" +#include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -395,6 +394,11 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL struct MiterPass : public Pass { MiterPass() : Pass("miter", "automatically create a miter circuit") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index 3075ef3f0..43373ce0e 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #include "kernel/sigtools.h" USING_YOSYS_NAMESPACE @@ -728,6 +729,11 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one) struct MutatePass : public Pass { MutatePass() : Pass("mutate", "generate or apply design mutations") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index db6836ea1..7a7a31806 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #include "kernel/consteval.h" #include "qbfsat.h" @@ -504,6 +505,11 @@ QbfSolveOptions parse_args(const std::vector &args) { struct QbfSatPass : public Pass { QbfSatPass() : Pass("qbfsat", "solve a 2QBF-SAT problem in the circuit") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/recover_names.cc b/passes/sat/recover_names.cc index cddd8771c..7ed8b1304 100644 --- a/passes/sat/recover_names.cc +++ b/passes/sat/recover_names.cc @@ -23,6 +23,7 @@ #include "kernel/celltypes.h" #include "kernel/utils.h" #include "kernel/satgen.h" +#include "kernel/log_help.h" #include #include @@ -690,6 +691,11 @@ struct RecoverNamesWorker { struct RecoverNamesPass : public Pass { RecoverNamesPass() : Pass("recover_names", "Execute a lossy mapping command and recover original netnames") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/opt"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 0c2143fc9..2f20880cb 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -21,17 +21,12 @@ // Niklas Een and Niklas Sörensson (2003) // http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.4.8161 -#include "kernel/register.h" #include "kernel/celltypes.h" #include "kernel/consteval.h" #include "kernel/sigtools.h" -#include "kernel/log.h" #include "kernel/satgen.h" -#include -#include -#include -#include -#include +#include "kernel/yosys.h" +#include "kernel/log_help.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -902,6 +897,11 @@ void print_qed() struct SatPass : public Pass { SatPass() : Pass("sat", "solve a SAT problem in the circuit") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc index 38dbd3cf9..f1b3ad09c 100644 --- a/passes/sat/supercover.cc +++ b/passes/sat/supercover.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "kernel/log_help.h" #include "kernel/sigtools.h" USING_YOSYS_NAMESPACE @@ -25,6 +26,11 @@ PRIVATE_NAMESPACE_BEGIN struct SupercoverPass : public Pass { SupercoverPass() : Pass("supercover", "add hi/lo cover cells for each wire bit") { } + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index 5553abec2..4703e4ad7 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -18,7 +18,9 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ + #include "kernel/yosys.h" +#include "kernel/log_help.h" YOSYS_NAMESPACE_BEGIN @@ -179,7 +181,13 @@ void SynthPropWorker::run() struct SyntProperties : public Pass { SyntProperties() : Pass("synthprop", "synthesize SVA properties") { } - virtual void help() + bool formatted_help() override { + auto *help = PrettyHelp::get_current(); + help->set_group("formal"); + return false; + } + + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -208,7 +216,7 @@ struct SyntProperties : public Pass { log("\n"); } - virtual void execute(std::vector args, RTLIL::Design* design) + void execute(std::vector args, RTLIL::Design* design) override { log_header(design, "Executing SYNTHPROP pass.\n"); SynthPropWorker worker(design); diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index c9fe98a74..91b3b563a 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -1,5 +1,4 @@ -OBJS += passes/techmap/flatten.o OBJS += passes/techmap/techmap.o OBJS += passes/techmap/simplemap.o OBJS += passes/techmap/dfflibmap.o diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index d00fee83b..409ac7865 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -92,7 +92,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std auto expr = attr->value; auto cell_name = cell->args[0]; - for (size_t pos = expr.find_first_of("\" \t"); pos != std::string::npos; pos = expr.find_first_of("\" \t")) + for (size_t pos = expr.find_first_of("\"\t"); pos != std::string::npos; pos = expr.find_first_of("\"\t")) expr.erase(pos, 1); // if this isn't an enable flop, the next_state variable is usually just the input pin name. @@ -117,6 +117,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std // the next_state variable isn't just a pin name; perhaps this is an enable? auto helper = LibertyExpression::Lexer(expr); auto tree = LibertyExpression::parse(helper); + // log_debug("liberty expression:\n%s\n", tree.str().c_str()); if (tree.kind == LibertyExpression::Kind::EMPTY) { if (!warned_cells.count(cell_name)) { @@ -392,9 +393,21 @@ static void find_cell_sr(std::vector cells, IdString cell_ty continue; if (!parse_next_state(cell, ff->find("next_state"), cell_next_pin, cell_next_pol, cell_enable_pin, cell_enable_pol)) continue; - if (!parse_pin(cell, ff->find("preset"), cell_set_pin, cell_set_pol) || cell_set_pol != setpol) + + if (!parse_pin(cell, ff->find("preset"), cell_set_pin, cell_set_pol)) continue; - if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol) || cell_clr_pol != clrpol) + if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol)) + continue; + if (!cell_next_pol) { + // next_state is negated + // we later propagate this inversion to the output, + // which requires the swap of set and reset + std::swap(cell_set_pin, cell_clr_pin); + std::swap(cell_set_pol, cell_clr_pol); + } + if (cell_set_pol != setpol) + continue; + if (cell_clr_pol != clrpol) continue; std::map this_cell_ports; @@ -432,12 +445,14 @@ static void find_cell_sr(std::vector cells, IdString cell_ty for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t")) value.erase(pos, 1); if (value == ff->args[0]) { + // next_state negation propagated to output this_cell_ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q'; if (cell_next_pol) found_noninv_output = true; found_output = true; } else if (value == ff->args[1]) { + // next_state negation propagated to output this_cell_ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q'; if (!cell_next_pol) found_noninv_output = true; diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index 85ed35ea1..c6f87b60b 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -163,6 +163,12 @@ void LibertyAst::dump(FILE *f, sieve &blacklist, sieve &whitelist, std::string i } #ifndef FILTERLIB + +// binary operators excluding ' ' +bool LibertyExpression::is_nice_binop(char c) { + return c == '*' || c == '&' || c == '^' || c == '+' || c == '|'; +} + // https://matklad.github.io/2020/04/13/simple-but-powerful-pratt-parsing.html LibertyExpression LibertyExpression::parse(Lexer &s, int min_prio) { if (s.empty()) @@ -201,15 +207,8 @@ LibertyExpression LibertyExpression::parse(Lexer &s, int min_prio) { while (true) { if (s.empty()) break; - - c = s.peek(); - while (isspace(c)) { - if (s.empty()) - return lhs; - s.next(); - c = s.peek(); - } + c = s.peek(); if (c == '\'') { // postfix NOT if (min_prio > 7) @@ -235,13 +234,31 @@ LibertyExpression LibertyExpression::parse(Lexer &s, int min_prio) { lhs = std::move(n); continue; - } else if (c == '&' || c == '*') { // infix AND - // technically space should be considered infix AND. it seems rare in practice. + } else if (c == '&' || c == '*' || isspace(c)) { // infix AND if (min_prio > 3) break; - s.next(); + + if (isspace(c)) { + // Rewind past this space and any further spaces + while (isspace(c)) { + if (s.empty()) + return lhs; + s.next(); + c = s.peek(); + } + if (is_nice_binop(c)) { + // We found a real binop, so this space wasn't an AND + // and we just discard it as meaningless whitespace + continue; + } + } else { + // Rewind past this op + s.next(); + } auto rhs = parse(s, 4); + if (rhs.kind == EMPTY) + continue; auto n = LibertyExpression{}; n.kind = Kind::AND; n.children.push_back(lhs); @@ -306,6 +323,45 @@ bool LibertyExpression::eval(dict& values) { } return false; } + +std::string LibertyExpression::str(int indent) +{ + std::string prefix; + switch (kind) { + case AND: + prefix += "(and "; + break; + case OR: + prefix += "(or "; + break; + case NOT: + prefix += "(not "; + break; + case XOR: + prefix += "(xor "; + break; + case PIN: + prefix += "(pin \"" + name + "\""; + break; + case EMPTY: + prefix += "("; + break; + default: + log_assert(false); + } + size_t add_indent = prefix.length(); + bool first = true; + for (auto child : children) { + if (!first) { + prefix += "\n" + std::string(indent + add_indent, ' '); + } + prefix += child.str(indent + add_indent); + first = false; + } + prefix += ")"; + return prefix; +} + #endif int LibertyParser::lexer(std::string &str) diff --git a/passes/techmap/libparse.h b/passes/techmap/libparse.h index 949adbdcf..ee0f3db42 100644 --- a/passes/techmap/libparse.h +++ b/passes/techmap/libparse.h @@ -26,6 +26,11 @@ #include #include +/** + * This file is likely to change in the near future. + * Rely on it in your plugins at your own peril + */ + namespace Yosys { struct LibertyAst @@ -88,6 +93,9 @@ namespace Yosys static LibertyExpression parse(Lexer &s, int min_prio = 0); void get_pin_names(pool& names); bool eval(dict& values); + std::string str(int indent = 0); + private: + static bool is_nice_binop(char c); }; class LibertyInputStream { diff --git a/passes/tests/Makefile.inc b/passes/tests/Makefile.inc index 531943d78..25e11967c 100644 --- a/passes/tests/Makefile.inc +++ b/passes/tests/Makefile.inc @@ -2,4 +2,5 @@ OBJS += passes/tests/test_autotb.o OBJS += passes/tests/test_cell.o OBJS += passes/tests/test_abcloop.o +OBJS += passes/tests/raise_error.o diff --git a/passes/tests/raise_error.cc b/passes/tests/raise_error.cc new file mode 100644 index 000000000..588a40806 --- /dev/null +++ b/passes/tests/raise_error.cc @@ -0,0 +1,103 @@ +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct RaiseErrorPass : public Pass { + RaiseErrorPass() : Pass("raise_error", "raise errors from attributes") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" raise_error [options] [selection]\n"); + log("\n"); + log("Test error handling by raising arbitrary errors. This pass iterates over the\n"); + log("design (or selection of it) checking for objects with the 'raise_error'\n"); + log("attribute set. Assigning 'raise_error' to a string more than one character long\n"); + log("will log that string as an error message before exiting. Assigning 'raise_error'\n"); + log("to an integer (less than 256) will exit with that value as the exit code.\n"); + log("\n"); + log(" -stderr\n"); + log(" Log error messages directly to stderr instead of using 'log_error'.\n"); + log("\n"); + log(" -always\n"); + log(" Raise an error even if the 'raise_error' attribute is missing.\n"); + log("\n"); + } + void execute(vector args, RTLIL::Design *design) override + { + log_header(design, "Executing RAISE_ERROR pass.\n"); + + bool use_stderr = false, always = false; + + int argidx; + for (argidx = 1; argidx < GetSize(args); argidx++) + { + if (args[argidx] == "-stderr") { + use_stderr = true; + continue; + } + if (args[argidx] == "-always") { + always = true; + continue; + } + break; + } + + extra_args(args, argidx, design, true); + + RTLIL::NamedObject *err_obj = nullptr; + + for (auto mod : design->all_selected_modules()) { + if (mod->has_attribute(ID::raise_error)) { + err_obj = mod->clone(); + break; + } + for (auto memb : mod->selected_members()) { + if (memb->has_attribute(ID::raise_error)) { + err_obj = memb; + break; + } + } + if (err_obj != nullptr) break; + } + + + if (err_obj == nullptr && !always) { + log("'raise_error' attribute not found\n"); + return; + } + + int err_no = 1; + string err_msg = ""; + if (err_obj != nullptr) { + log("Raising error from '%s'.\n", log_id(err_obj)); + err_no = err_obj->attributes[ID::raise_error].as_int(); + if (err_no > 256) { + err_msg = err_obj->get_string_attribute(ID::raise_error); + err_no = 1; + } + } else { + err_msg = "No 'raise_error' attribute found"; + } + + if (err_msg.size() > 0) { + if (use_stderr) { + std::cerr << err_msg << std::endl; + } else { + log_error("%s\n", err_msg.c_str()); + } + } + + if (err_no < 256) { + log_flush(); + #if defined(_MSC_VER) + _exit(err_no); + #else + _Exit(err_no); + #endif + } + } +} RaiseErrorPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc index 9e7adaab1..ed54ce164 100644 --- a/passes/tests/test_abcloop.cc +++ b/passes/tests/test_abcloop.cc @@ -243,7 +243,9 @@ static void test_abcloop() } struct TestAbcloopPass : public Pass { - TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { } + TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { + internal(); + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 404d1e48d..306e760ee 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -326,7 +326,9 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s } struct TestAutotbBackend : public Backend { - TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { } + TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { + internal(); + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index a34eafc2f..b6385766c 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -705,7 +705,9 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: } struct TestCellPass : public Pass { - TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { } + TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { + internal(); + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 74a484d59..8b4561c34 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -47,6 +47,11 @@ struct SynthPass : public ScriptPass { log(" flatten the design before synthesis. this will pass '-auto-top' to\n"); log(" 'hierarchy' if no top module is specified.\n"); log("\n"); + log(" -hieropt\n"); + log(" enable hierarchical optimization. this option is useful when `-flatten'\n"); + log(" is not used, or when selected modules are marked with 'keep_hierarchy'\n."); + log(" to prevent their dissolution.\n"); + log("\n"); log(" -encfile \n"); log(" passed to 'fsm_recode' via 'fsm'\n"); log("\n"); @@ -99,7 +104,7 @@ struct SynthPass : public ScriptPass { } string top_module, fsm_opts, memory_opts, abc; - bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth; + bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt; int lut; std::vector techmap_maps; @@ -118,6 +123,7 @@ struct SynthPass : public ScriptPass { noshare = false; flowmap = false; booth = false; + hieropt = false; abc = "abc"; techmap_maps.clear(); } @@ -201,6 +207,10 @@ struct SynthPass : public ScriptPass { techmap_maps.push_back(args[++argidx]); continue; } + if (args[argidx] == "-hieropt") { + hieropt = true; + continue; + } break; } extra_args(args, argidx, design); @@ -223,6 +233,12 @@ struct SynthPass : public ScriptPass { void script() override { + std::string hieropt_flag; + if (help_mode) + hieropt_flag = " [-hier]"; + else + hieropt_flag = hieropt ? " -hier" : ""; + if (check_label("begin")) { if (help_mode) { run("hierarchy -check [-top | -auto-top]"); @@ -247,7 +263,7 @@ struct SynthPass : public ScriptPass { run("opt -nodffe -nosdff"); if (!nofsm || help_mode) run("fsm" + fsm_opts, " (unless -nofsm)"); - run("opt"); + run("opt" + hieropt_flag); run("wreduce"); run("peepopt"); run("opt_clean"); @@ -261,13 +277,13 @@ struct SynthPass : public ScriptPass { run("alumacc", " (unless -noalumacc)"); if (!noshare) run("share", " (unless -noshare)"); - run("opt"); + run("opt" + hieropt_flag); run("memory -nomap" + memory_opts); run("opt_clean"); } if (check_label("fine")) { - run("opt -fast -full"); + run("opt -fast -full" + hieropt_flag); run("memory_map"); run("opt -full"); if (help_mode) { @@ -291,7 +307,7 @@ struct SynthPass : public ScriptPass { } else if (flowmap) { run(stringf("flowmap -maxlut %d", lut)); } - run("opt -fast"); + run("opt -fast" + hieropt_flag); if ((!noabc && !flowmap) || help_mode) { #ifdef YOSYS_ENABLE_ABC diff --git a/techlibs/xilinx/tests/.gitignore b/techlibs/xilinx/tests/.gitignore index 0d9c28fde..7cb771190 100644 --- a/techlibs/xilinx/tests/.gitignore +++ b/techlibs/xilinx/tests/.gitignore @@ -1,7 +1,6 @@ bram1_cmp bram1.mk bram1_[0-9]*/ -bram2.log bram2_syn.v bram2_tb dsp_work*/ diff --git a/tests/opt/.gitignore b/tests/.gitignore similarity index 60% rename from tests/opt/.gitignore rename to tests/.gitignore index 8355de9dc..d8e01e026 100644 --- a/tests/opt/.gitignore +++ b/tests/.gitignore @@ -1,2 +1,4 @@ *.log +*.out +*.err run-test.mk diff --git a/tests/aiger/.gitignore b/tests/aiger/.gitignore index 54b4a279b..4bb3e67f6 100644 --- a/tests/aiger/.gitignore +++ b/tests/aiger/.gitignore @@ -1,3 +1,2 @@ /*_ref.v -/*.log /neg.out/ diff --git a/tests/arch/anlogic/.gitignore b/tests/arch/anlogic/.gitignore index 9a71dca69..d9f7e276c 100644 --- a/tests/arch/anlogic/.gitignore +++ b/tests/arch/anlogic/.gitignore @@ -1,4 +1,2 @@ -*.log -/run-test.mk +*_synth.v +*_testbench diff --git a/tests/arch/ecp5/.gitignore b/tests/arch/ecp5/.gitignore deleted file mode 100644 index 1d329c933..000000000 --- a/tests/arch/ecp5/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.log -/run-test.mk diff --git a/tests/arch/efinix/.gitignore b/tests/arch/efinix/.gitignore deleted file mode 100644 index b48f808a1..000000000 --- a/tests/arch/efinix/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/*.log -/*.out -/run-test.mk diff --git a/tests/arch/fabulous/.gitignore b/tests/arch/fabulous/.gitignore index 9a71dca69..d9f7e276c 100644 --- a/tests/arch/fabulous/.gitignore +++ b/tests/arch/fabulous/.gitignore @@ -1,4 +1,2 @@ -*.log -/run-test.mk +*_synth.v +*_testbench diff --git a/tests/arch/gatemate/.gitignore b/tests/arch/gatemate/.gitignore index 9a71dca69..d9f7e276c 100644 --- a/tests/arch/gatemate/.gitignore +++ b/tests/arch/gatemate/.gitignore @@ -1,4 +1,2 @@ -*.log -/run-test.mk +*_synth.v +*_testbench diff --git a/tests/arch/gowin/.gitignore b/tests/arch/gowin/.gitignore deleted file mode 100644 index b48f808a1..000000000 --- a/tests/arch/gowin/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/*.log -/*.out -/run-test.mk diff --git a/tests/arch/ice40/.gitignore b/tests/arch/ice40/.gitignore index 54f908bdb..a86b36792 100644 --- a/tests/arch/ice40/.gitignore +++ b/tests/arch/ice40/.gitignore @@ -1,5 +1,3 @@ -*.log *.json -/run-test.mk +*_synth.v +*_testbench diff --git a/tests/arch/intel_alm/.gitignore b/tests/arch/intel_alm/.gitignore deleted file mode 100644 index ba42e1ee6..000000000 --- a/tests/arch/intel_alm/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/*.log -/run-test.mk diff --git a/tests/arch/machxo2/.gitignore b/tests/arch/machxo2/.gitignore deleted file mode 100644 index 1d329c933..000000000 --- a/tests/arch/machxo2/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.log -/run-test.mk diff --git a/tests/arch/microchip/.gitignore b/tests/arch/microchip/.gitignore index 9c0a77944..aae26dc02 100644 --- a/tests/arch/microchip/.gitignore +++ b/tests/arch/microchip/.gitignore @@ -1,4 +1,2 @@ -*.log -/run-test.mk *.vm diff --git a/tests/arch/nanoxplore/.gitignore b/tests/arch/nanoxplore/.gitignore deleted file mode 100644 index 1d329c933..000000000 --- a/tests/arch/nanoxplore/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.log -/run-test.mk diff --git a/tests/arch/nexus/.gitignore b/tests/arch/nexus/.gitignore deleted file mode 100644 index ba42e1ee6..000000000 --- a/tests/arch/nexus/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/*.log -/run-test.mk diff --git a/tests/arch/quicklogic/.gitignore b/tests/arch/quicklogic/.gitignore index ae20ed342..d9f7e276c 100644 --- a/tests/arch/quicklogic/.gitignore +++ b/tests/arch/quicklogic/.gitignore @@ -1,4 +1,2 @@ -*.log -run-test.mk +*_synth.v +*_testbench diff --git a/tests/arch/quicklogic/pp3/fsm.ys b/tests/arch/quicklogic/pp3/fsm.ys index 418db8025..9679628e9 100644 --- a/tests/arch/quicklogic/pp3/fsm.ys +++ b/tests/arch/quicklogic/pp3/fsm.ys @@ -11,8 +11,8 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module -select -assert-count 1 t:LUT2 -select -assert-count 9 t:LUT3 +select -assert-count 2 t:LUT2 +select -assert-count 4 t:LUT3 select -assert-count 4 t:dffepc select -assert-count 1 t:logic_0 select -assert-count 1 t:logic_1 @@ -20,4 +20,4 @@ select -assert-count 3 t:inpad select -assert-count 2 t:outpad select -assert-count 1 t:ckpad -select -assert-none t:LUT2 t:LUT3 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D +select -assert-none t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D diff --git a/tests/arch/xilinx/.gitignore b/tests/arch/xilinx/.gitignore index c99b79371..15a12d049 100644 --- a/tests/arch/xilinx/.gitignore +++ b/tests/arch/xilinx/.gitignore @@ -1,5 +1,3 @@ -/*.log -/*.out /run-test.mk /*_uut.v /test_macc diff --git a/tests/asicworld/.gitignore b/tests/asicworld/.gitignore deleted file mode 100644 index 073f46157..000000000 --- a/tests/asicworld/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.log -*.out diff --git a/tests/bind/.gitignore b/tests/bind/.gitignore deleted file mode 100644 index 8355de9dc..000000000 --- a/tests/bind/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.log -run-test.mk diff --git a/tests/blif/.gitignore b/tests/blif/.gitignore deleted file mode 100644 index 397b4a762..000000000 --- a/tests/blif/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.log diff --git a/tests/bugpoint/.gitignore b/tests/bugpoint/.gitignore new file mode 100644 index 000000000..1012c66cc --- /dev/null +++ b/tests/bugpoint/.gitignore @@ -0,0 +1,5 @@ +bugpoint-case.* +*.log +*.err +*.temp +run-test.mk diff --git a/tests/bugpoint/failures.ys b/tests/bugpoint/failures.ys new file mode 100644 index 000000000..ce8daa8cc --- /dev/null +++ b/tests/bugpoint/failures.ys @@ -0,0 +1,29 @@ +write_file fail.temp << EOF +logger -expect error "Missing -script or -command option." 1 +bugpoint -suffix fail -yosys ../../yosys +EOF +exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp + +write_file fail.temp << EOF +logger -expect error "do not crash on this design" 1 +bugpoint -suffix fail -yosys ../../yosys -command "dump" +EOF +exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp + +write_file fail.temp << EOF +logger -expect error "returned value 3 instead of expected 7" 1 +bugpoint -suffix fail -yosys ../../yosys -command raise_error -expect-return 7 +EOF +exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp + +write_file fail.temp << EOF +logger -expect error "not found in the log file!" 1 +bugpoint -suffix fail -yosys ../../yosys -command raise_error -grep "nope" +EOF +exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp + +write_file fail.temp << EOF +logger -expect error "not found in stderr log!" 1 +bugpoint -suffix fail -yosys ../../yosys -command raise_error -err-grep "nope" +EOF +exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp diff --git a/tests/bugpoint/mod_constraints.ys b/tests/bugpoint/mod_constraints.ys new file mode 100644 index 000000000..f35095510 --- /dev/null +++ b/tests/bugpoint/mod_constraints.ys @@ -0,0 +1,83 @@ +read_rtlil mods.il +select -assert-count 7 w:* +select -assert-mod-count 3 =* +select -assert-count 4 c:* +design -stash base + +# everything is removed by default +design -load base +bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 +select -assert-count 1 w:* +select -assert-mod-count 1 =* +select -assert-none c:* + +# don't remove wires +design -load base +bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -modules -cells +select -assert-count 3 w:* +select -assert-mod-count 1 =* +select -assert-none c:* + +# don't remove cells or their connections +design -load base +bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules +select -assert-count 5 w:* +select -assert-mod-count 1 =* +select -assert-count 4 c:* + +# don't remove cells but do remove their connections +design -load base +bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules -connections +select -assert-count 1 w:* +select -assert-mod-count 1 =* +select -assert-count 4 c:* + +# don't remove modules +design -load base +bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -cells +select -assert-count 1 w:* +select -assert-mod-count 3 =* +select -assert-none c:* + +# can keep wires +design -load base +setattr -set bugpoint_keep 1 w:w_b +bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 +select -assert-count 2 w:* +select -assert-mod-count 1 =* +select -assert-none c:* + +# a wire with keep won't keep the cell/module containing it +design -load base +setattr -set bugpoint_keep 1 w:w_o +bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 +select -assert-count 1 w:* +select -assert-mod-count 1 =* +select -assert-none c:* + +# can keep cells (and do it without the associated module) +design -load base +setattr -set bugpoint_keep 1 c:c_a +bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 +select -assert-count 1 w:* +select -assert-mod-count 1 =* +select -assert-count 1 c:* + +# can keep modules +design -load base +setattr -mod -set bugpoint_keep 1 m_a +bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 +select -assert-count 1 w:* +select -assert-mod-count 2 =* +select -assert-none c:* + +# minimize to just the path connecting w_a and w_c +# which happens via w_b, w_i, w_o, m_a, c_a and c_b +write_file script.temp << EOF +select -assert-none w:w_a %co* w:w_c %ci* %i +EOF +design -load base +bugpoint -suffix mods -yosys ../../yosys -script script.temp -grep "Assertion failed" +select -assert-count 5 w:* +select -assert-mod-count 2 =* +select -assert-count 2 c:* diff --git a/tests/bugpoint/mods.il b/tests/bugpoint/mods.il new file mode 100644 index 000000000..fe3ce6522 --- /dev/null +++ b/tests/bugpoint/mods.il @@ -0,0 +1,38 @@ +module \m_a + wire input 1 \w_i + wire output 2 \w_o + connect \w_o \w_i +end + +module \m_b + wire input 1 \w_i + wire output 2 \w_o +end + +attribute \top 1 +module \top + attribute \raise_error 3 + wire \w_a + wire \w_b + wire \w_c + + cell \m_a \c_a + connect \w_i \w_a + connect \w_o \w_b + end + + cell \m_a \c_b + connect \w_i \w_b + connect \w_o \w_c + end + + cell \m_b \c_c + connect \w_i \w_c + connect \w_o \w_a + end + + cell \m_b \c_d + connect \w_i 1'0 + connect \w_o 1'1 + end +end diff --git a/tests/bugpoint/proc_constraints.ys b/tests/bugpoint/proc_constraints.ys new file mode 100644 index 000000000..22b8b3c60 --- /dev/null +++ b/tests/bugpoint/proc_constraints.ys @@ -0,0 +1,49 @@ +read_rtlil procs.il +select -assert-count 2 p:* +design -stash err_q + +# processes get removed by default +design -load err_q +bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 +select -assert-none p:* + +# individual processes can be kept +design -load err_q +setattr -set bugpoint_keep 1 p:proc_a +bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 +select -assert-count 1 p:* + +# all processes can be kept +design -load err_q +bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -wires +select -assert-count 2 p:* + +# d and clock are connected after proc +design -load err_q +proc +select -assert-count 3 w:d %co +select -assert-count 3 w:clock %co + +# no assigns means no d +design -load err_q +bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -assigns +proc +select -assert-count 1 w:d %co + +# no updates means no clock +design -load err_q +bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -updates +proc +select -assert-count 1 w:clock %co + +# can remove ports +design -load err_q +select -assert-count 5 x:* +bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports +select -assert-none x:* + +# can keep ports +design -load err_q +setattr -set bugpoint_keep 1 i:d o:q +bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports +select -assert-count 2 x:* diff --git a/tests/bugpoint/procs.il b/tests/bugpoint/procs.il new file mode 100644 index 000000000..cb9f7c8dd --- /dev/null +++ b/tests/bugpoint/procs.il @@ -0,0 +1,42 @@ +module \ff_with_en_and_sync_reset + wire $0\q[1:1] + wire $0\q[0:0] + attribute \raise_error 4 + wire width 2 output 5 \q + wire width 2 input 4 \d + wire input 3 \enable + wire input 2 \reset + wire input 1 \clock + + process \proc_a + assign $0\q[0:0] \q [0] + switch \reset + case 1'1 + assign $0\q[0:0] 1'0 + case + switch \enable + case 1'1 + assign $0\q[0:0] \d [0] + case + end + end + sync posedge \clock + update \q [0] $0\q[0:0] + end + + process \proc_b + assign $0\q[1:1] \q [1] + switch \reset + case 1'1 + assign $0\q[1:1] 1'0 + case + switch \enable + case 1'1 + assign $0\q[1:1] \d [1] + case + end + end + sync posedge \clock + update \q [1] $0\q[1:1] + end +end diff --git a/tests/bugpoint/raise_error.ys b/tests/bugpoint/raise_error.ys new file mode 100644 index 000000000..8fb10eb96 --- /dev/null +++ b/tests/bugpoint/raise_error.ys @@ -0,0 +1,60 @@ +read_verilog -noblackbox << EOF +(* raise_error=7 *) +module top(); +endmodule + +(* raise_error="help me" *) +module other(); +endmodule + +(* raise_error *) +module def(); +endmodule +EOF +select -assert-mod-count 3 =* +design -stash read + +# empty design does not raise_error +design -reset +logger -expect log "'raise_error' attribute not found" 1 +raise_error +logger -check-expected + +# raise_error with int exits with status +design -load read +bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 7 +select -assert-mod-count 1 =* +select -assert-mod-count 1 top + +# raise_error -always still uses 'raise_error' attribute if possible +design -load read +bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -expect-return 7 +select -assert-mod-count 1 =* +select -assert-mod-count 1 top + +# raise_error with string prints message and exits with 1 +design -load read +rename top abc +bugpoint -suffix error -yosys ../../yosys -command raise_error -grep "help me" -expect-return 1 +select -assert-mod-count 1 =* +select -assert-mod-count 1 other + +# raise_error with no value exits with 1 +design -load read +rename def zzy +delete other +bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 1 +select -assert-mod-count 1 =* +select -assert-mod-count 1 zzy + +# raise_error -stderr prints to stderr and exits with 1 +design -load read +rename top abc +bugpoint -suffix error -yosys ../../yosys -command "raise_error -stderr" -err-grep "help me" -expect-return 1 +select -assert-mod-count 1 =* +select -assert-mod-count 1 other + +# empty design can raise_error -always +design -reset +bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -grep "ERROR: No 'raise_error' attribute found" -expect-return 1 +bugpoint -suffix error -yosys ../../yosys -command "raise_error -always -stderr" -err-grep "No 'raise_error' attribute found" -expect-return 1 diff --git a/tests/bugpoint/run-test.sh b/tests/bugpoint/run-test.sh new file mode 100755 index 000000000..006c731e3 --- /dev/null +++ b/tests/bugpoint/run-test.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -eu +source ../gen-tests-makefile.sh +generate_mk --yosys-scripts diff --git a/tests/fmt/.gitignore b/tests/fmt/.gitignore index a36a15ec4..e6ae0d879 100644 --- a/tests/fmt/.gitignore +++ b/tests/fmt/.gitignore @@ -1,3 +1,2 @@ -*.log iverilog-* yosys-* diff --git a/tests/hana/.gitignore b/tests/hana/.gitignore deleted file mode 100644 index 073f46157..000000000 --- a/tests/hana/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.log -*.out diff --git a/tests/liberty/.gitignore b/tests/liberty/.gitignore index 2ee56e9d1..b312f8c50 100644 --- a/tests/liberty/.gitignore +++ b/tests/liberty/.gitignore @@ -1,3 +1,2 @@ -*.log /*.filtered *.verilogsim diff --git a/tests/lut/.gitignore b/tests/lut/.gitignore deleted file mode 100644 index 397b4a762..000000000 --- a/tests/lut/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.log diff --git a/tests/memlib/.gitignore b/tests/memlib/.gitignore index 03dbe82ae..bfa1a801e 100644 --- a/tests/memlib/.gitignore +++ b/tests/memlib/.gitignore @@ -1,5 +1,2 @@ -t_*.log -t_*.out t_*.v t_*.ys -run-test.mk diff --git a/tests/memories/.gitignore b/tests/memories/.gitignore index 90a0983a6..14e98cead 100644 --- a/tests/memories/.gitignore +++ b/tests/memories/.gitignore @@ -1,3 +1 @@ -*.log -*.out *.dmp diff --git a/tests/opt/opt_hier.tcl b/tests/opt/opt_hier.tcl new file mode 100644 index 000000000..65d8f9809 --- /dev/null +++ b/tests/opt/opt_hier.tcl @@ -0,0 +1,34 @@ +yosys -import + +# per each opt_hier_*.v source file, confirm flattening and hieropt+flattening +# are combinationally equivalent +foreach fn [glob opt_hier_*.v] { + log -header "Test $fn" + log -push + design -reset + + read_verilog $fn + hierarchy -auto-top + prep -top top + design -save start + flatten + design -save gold + design -load start + opt -hier + # check any instances marked `should_get_optimized_out` were + # indeed optimized out + select -assert-none a:should_get_optimized_out + dump + flatten + design -save gate + + design -reset + design -copy-from gold -as gold A:top + design -copy-from gate -as gate A:top + yosys rename -hide + equiv_make gold gate equiv + equiv_induct equiv + equiv_status -assert equiv + + log -pop +} diff --git a/tests/opt/opt_hier_simple1.v b/tests/opt/opt_hier_simple1.v new file mode 100644 index 000000000..17935a960 --- /dev/null +++ b/tests/opt/opt_hier_simple1.v @@ -0,0 +1,8 @@ +module m(input a, output y1, output y2); + assign y1 = a; + assign y2 = a; +endmodule + +module top(input a, output y2, output y1); + m inst(.a(a), .y1(y1), .y2(y2)); +endmodule diff --git a/tests/opt/opt_hier_simple2.v b/tests/opt/opt_hier_simple2.v new file mode 100644 index 000000000..9e724216b --- /dev/null +++ b/tests/opt/opt_hier_simple2.v @@ -0,0 +1,7 @@ +module m(input [3:0] i, output [3:0] y); + assign y = i + 1; +endmodule + +module top(output [3:0] y); + m inst(.i(4), .y(y)); +endmodule diff --git a/tests/opt/opt_hier_test1.v b/tests/opt/opt_hier_test1.v new file mode 100644 index 000000000..69de6b92f --- /dev/null +++ b/tests/opt/opt_hier_test1.v @@ -0,0 +1,22 @@ +(* blackbox *) +module bb(output y); +endmodule + +// all instances of `m` tie together a[1], a[2] +// this can be used to conclude y[0]=0 +module m(input [3:0] a, output [1:0] y, output x); + assign y[0] = a[1] != a[2]; + assign x = a[0] ^ a[3]; + (* should_get_optimized_out *) + bb bb1(.y(y[1])); +endmodule + +module top(input j, output z, output [2:0] x); + wire [1:0] y1; + wire [1:0] y2; + wire [1:0] y3; + m inst1(.a(0), .y(y1), .x(x[0])); + m inst2(.a(15), .y(y2), .x(x[1])); + m inst3(.a({1'b1, j, j, 1'b0}), .y(y3), .x(x[2])); + assign z = (&y1) ^ (&y2) ^ (&y3); +endmodule diff --git a/tests/opt/run-test.sh b/tests/opt/run-test.sh index 006c731e3..1d1d9b7a6 100755 --- a/tests/opt/run-test.sh +++ b/tests/opt/run-test.sh @@ -1,4 +1,4 @@ #!/usr/bin/env bash set -eu source ../gen-tests-makefile.sh -generate_mk --yosys-scripts +generate_mk --yosys-scripts --tcl-scripts diff --git a/tests/peepopt/.gitignore b/tests/peepopt/.gitignore deleted file mode 100644 index 50e13221d..000000000 --- a/tests/peepopt/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/*.log diff --git a/tests/proc/.gitignore b/tests/proc/.gitignore deleted file mode 100644 index 397b4a762..000000000 --- a/tests/proc/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.log diff --git a/tests/rpc/.gitignore b/tests/rpc/.gitignore deleted file mode 100644 index 397b4a762..000000000 --- a/tests/rpc/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.log diff --git a/tests/sat/.gitignore b/tests/sat/.gitignore index 664425d73..3fa128fcc 100644 --- a/tests/sat/.gitignore +++ b/tests/sat/.gitignore @@ -1,4 +1,2 @@ -*.log -run-test.mk *.vcd *.fst diff --git a/tests/select/.gitignore b/tests/select/.gitignore deleted file mode 100644 index 50e13221d..000000000 --- a/tests/select/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/*.log diff --git a/tests/sim/.gitignore b/tests/sim/.gitignore index 2c96b65f8..769b314cd 100644 --- a/tests/sim/.gitignore +++ b/tests/sim/.gitignore @@ -1,6 +1,3 @@ -*.log -/run-test.mk +*_synth.v +*_testbench -*.out *.fst diff --git a/tests/simple/.gitignore b/tests/simple/.gitignore deleted file mode 100644 index 5daaadbd7..000000000 --- a/tests/simple/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -*.log -*.out -*.err diff --git a/tests/simple_abc9/.gitignore b/tests/simple_abc9/.gitignore index fda60e577..e31b7dc7f 100644 --- a/tests/simple_abc9/.gitignore +++ b/tests/simple_abc9/.gitignore @@ -1,5 +1,3 @@ *.v *.sv -*.log -*.out *.bak diff --git a/tests/svtypes/.gitignore b/tests/svtypes/.gitignore deleted file mode 100644 index b48f808a1..000000000 --- a/tests/svtypes/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/*.log -/*.out -/run-test.mk diff --git a/tests/techmap/.gitignore b/tests/techmap/.gitignore deleted file mode 100644 index 56c9ba8f9..000000000 --- a/tests/techmap/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -*.log -*.out -/*.mk diff --git a/tests/techmap/dfflibmap.lib b/tests/techmap/dfflibmap.lib index d0cd472c3..54a44a296 100644 --- a/tests/techmap/dfflibmap.lib +++ b/tests/techmap/dfflibmap.lib @@ -55,7 +55,7 @@ library(test) { cell (dffe) { area : 6; ff("IQ", "IQN") { - next_state : "(D&EN) | (IQ&!EN)"; + next_state : "(D EN) | (IQ !EN)"; clocked_on : "!CLK"; } pin(D) { diff --git a/tests/techmap/dfflibmap.ys b/tests/techmap/dfflibmap.ys index 77488d60f..822d87a36 100644 --- a/tests/techmap/dfflibmap.ys +++ b/tests/techmap/dfflibmap.ys @@ -81,3 +81,19 @@ clean select -assert-count 0 t:dffn select -assert-count 5 t:dffsr select -assert-count 1 t:dffe + +design -load orig +dfflibmap -liberty dfflibmap.lib -liberty dfflibmap_dffsr_mixedpol.lib -dont_use dffsr +clean +# We have one more _NOT_ than with the regular dffsr +select -assert-count 6 t:$_NOT_ +select -assert-count 1 t:dffn +select -assert-count 4 t:dffsr_mixedpol +select -assert-count 1 t:dffe +# The additional NOT is on ff2. +# Originally, ff2.R is an active high "set". +# dffsr_mixedpol has functionally swapped labels due to the next_state inversion, +# so we use its CLEAR port for the "set", +# but we have to invert it because the CLEAR pin is active low. +# ff2.CLEAR = !R +select -assert-count 1 c:ff2 %x:+[CLEAR] %ci t:$_NOT_ %i diff --git a/tests/techmap/dfflibmap_dffr_not_next.lib b/tests/techmap/dfflibmap_dffr_not_next.lib new file mode 100644 index 000000000..74004bea1 --- /dev/null +++ b/tests/techmap/dfflibmap_dffr_not_next.lib @@ -0,0 +1,33 @@ +library(test) { + cell (dffr_not_next) { + area : 6; + ff("IQ", "IQN") { + next_state : "!D"; + clocked_on : "CLK"; + clear : "CLEAR"; + preset : "PRESET"; + clear_preset_var1 : L; + clear_preset_var2 : L; + } + pin(D) { + direction : input; + } + pin(CLK) { + direction : input; + } + pin(CLEAR) { + direction : input; + } + pin(PRESET) { + direction : input; + } + pin(Q) { + direction: output; + function : "IQ"; + } + pin(QN) { + direction: output; + function : "IQN"; + } + } +} diff --git a/tests/techmap/dfflibmap_dffsr_mixedpol.lib b/tests/techmap/dfflibmap_dffsr_mixedpol.lib new file mode 100644 index 000000000..8c6a2f509 --- /dev/null +++ b/tests/techmap/dfflibmap_dffsr_mixedpol.lib @@ -0,0 +1,35 @@ +library(test) { + cell (dffsr_mixedpol) { + area : 6; + ff("IQ", "IQN") { + // look here + next_state : "!D"; + clocked_on : "CLK"; + // look here + clear : "!CLEAR"; + preset : "PRESET"; + clear_preset_var1 : L; + clear_preset_var2 : L; + } + pin(D) { + direction : input; + } + pin(CLK) { + direction : input; + } + pin(CLEAR) { + direction : input; + } + pin(PRESET) { + direction : input; + } + pin(Q) { + direction: output; + function : "IQ"; + } + pin(QN) { + direction: output; + function : "IQN"; + } + } +} diff --git a/tests/techmap/dfflibmap_dffsr_not_next.lib b/tests/techmap/dfflibmap_dffsr_not_next.lib new file mode 100644 index 000000000..579dedb10 --- /dev/null +++ b/tests/techmap/dfflibmap_dffsr_not_next.lib @@ -0,0 +1,28 @@ +library (test_not_next) { + cell (dffsr_not_next) { + area : 1.0; + pin (Q) { + direction : output; + function : "STATE"; + } + pin (CLK) { + clock : true; + direction : input; + } + pin (D) { + direction : input; + } + pin (RN) { + direction : input; + } + pin (SN) { + direction : input; + } + ff (STATE,STATEN) { + clear : "!SN"; + clocked_on : "CLK"; + next_state : "!D"; + preset : "!RN"; + } + } +} \ No newline at end of file diff --git a/tests/techmap/dfflibmap_formal.ys b/tests/techmap/dfflibmap_formal.ys new file mode 100644 index 000000000..11c90ea6c --- /dev/null +++ b/tests/techmap/dfflibmap_formal.ys @@ -0,0 +1,116 @@ +################################################################## + +read_verilog -sv -icells < + +#include "kernel/io.h" + +YOSYS_NAMESPACE_BEGIN + +TEST(KernelStringfTest, integerTruncation) +{ + EXPECT_EQ(stringf("%d", 1LL << 32), "0"); + EXPECT_EQ(stringf("%u", 1LL << 32), "0"); + EXPECT_EQ(stringf("%x", 0xff12345678LL), "12345678"); + EXPECT_EQ(stringf("%hu", 0xff12345678LL), "22136"); +} + +TEST(KernelStringfTest, charFormat) +{ + EXPECT_EQ(stringf("%c", 256), std::string_view("\0", 1)); + EXPECT_EQ(stringf("%c", -1), "\377"); +} + +TEST(KernelStringfTest, floatFormat) +{ + EXPECT_EQ(stringf("%g", 1.0), "1"); +} + +TEST(KernelStringfTest, intToFloat) +{ + EXPECT_EQ(stringf("%g", 1), "1"); +} + +TEST(KernelStringfTest, floatToInt) +{ + EXPECT_EQ(stringf("%d", 1.0), "1"); + EXPECT_EQ(stringf("%d", -1.6), "-1"); +} + +TEST(KernelStringfTest, stringParam) +{ + EXPECT_EQ(stringf("%s", std::string("hello")), "hello"); +} + +TEST(KernelStringfTest, stringViewParam) +{ + EXPECT_EQ(stringf("%s", std::string_view("hello")), "hello"); +} + +TEST(KernelStringfTest, escapePercent) +{ + EXPECT_EQ(stringf("%%"), "%"); +} + +TEST(KernelStringfTest, trailingPercent) +{ + EXPECT_EQ(stringf("%"), "%"); +} + +TEST(KernelStringfTest, dynamicWidth) +{ + EXPECT_EQ(stringf("%*s", 8, "hello"), " hello"); +} + +TEST(KernelStringfTest, dynamicPrecision) +{ + EXPECT_EQ(stringf("%.*f", 4, 1.0), "1.0000"); +} + +TEST(KernelStringfTest, dynamicWidthAndPrecision) +{ + EXPECT_EQ(stringf("%*.*f", 8, 4, 1.0), " 1.0000"); +} + +YOSYS_NAMESPACE_END diff --git a/tests/unit/techmap/libparseTest.cc b/tests/unit/techmap/libparseTest.cc new file mode 100644 index 000000000..b58e55bf2 --- /dev/null +++ b/tests/unit/techmap/libparseTest.cc @@ -0,0 +1,88 @@ +#include +#include "passes/techmap/libparse.h" + +YOSYS_NAMESPACE_BEGIN + +namespace RTLIL { + + class TechmapLibparseTest : public testing::Test { + protected: + TechmapLibparseTest() { + if (log_files.empty()) log_files.emplace_back(stdout); + } + void checkAll(std::initializer_list expressions, std::string expected) { + for (const auto& e : expressions) { + auto helper = LibertyExpression::Lexer(e); + auto tree_s = LibertyExpression::parse(helper).str(); + EXPECT_EQ(tree_s, expected); + } + } + }; + TEST_F(TechmapLibparseTest, LibertyExpressionSpace) + { + checkAll({ + "x", + "x ", + " x", + " x ", + " x ", + }, "(pin \"x\")"); + + checkAll({ + "x y", + " x y ", + "x (y)", + " x (y) ", + "(x) y", + " (x) y ", + + "x & y", + "x&y", + "x &y", + "x& y", + " x&y ", + "x & (y)", + "x&(y)", + "x &(y)", + "x& (y)", + " x&(y) ", + "(x) & y", + "(x)&y", + "(x) &y", + "(x)& y", + " (x)&y ", + }, "(and (pin \"x\")\n" + " (pin \"y\"))" + ); + + checkAll({ + "x ^ y", + "x^y", + "x ^y", + "x^ y", + " x^y ", + }, "(xor (pin \"x\")\n" + " (pin \"y\"))" + ); + checkAll({ + "x !y", + " x !y ", + "x & !y", + "x&!y", + "x &!y", + "x& !y", + " x&!y ", + "x y'", + " x y' ", + "x & y'", + "x&y'", + "x &y'", + "x& y'", + " x&y' ", + }, "(and (pin \"x\")\n" + " (not (pin \"y\")))" + ); + } +} + +YOSYS_NAMESPACE_END diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 3dbd50843..879645f66 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -1,9 +1,6 @@ -/*.log -/*.out /*.sel /write_gzip.v /write_gzip.v.gz -/run-test.mk /plugin.so /plugin.so.dSYM /temp diff --git a/tests/various/chformal_check.ys b/tests/various/chformal_check.ys index 951543fa5..2b2d292e4 100644 --- a/tests/various/chformal_check.ys +++ b/tests/various/chformal_check.ys @@ -36,6 +36,12 @@ select -assert-count 1 t:$assert design -load prep +chformal -assert2cover + +select -assert-count 1 t:$check r:FLAVOR=cover %i + +design -load prep + chformal -assert2assume async2sync chformal -lower @@ -66,3 +72,8 @@ design -copy-from gate -as gate top miter -equiv -flatten -make_assert gold gate miter sat -verify -prove-asserts -tempinduct miter + +design -load prep + +logger -expect error "Cannot use both" 1 +chformal -assert2assume -assert2cover diff --git a/tests/various/lcov.gold b/tests/various/lcov.gold new file mode 100644 index 000000000..b9a87ed94 --- /dev/null +++ b/tests/various/lcov.gold @@ -0,0 +1,44 @@ +SF:lcov.v +DA:2,1 +DA:3,1 +DA:4,1 +DA:5,1 +DA:6,1 +DA:7,1 +DA:8,1 +DA:9,0 +DA:13,1 +DA:14,1 +DA:17,1 +DA:18,1 +DA:19,1 +DA:21,0 +DA:22,0 +DA:23,0 +DA:24,0 +DA:25,0 +DA:26,0 +DA:27,0 +DA:28,0 +DA:29,0 +DA:30,0 +DA:32,1 +DA:33,1 +DA:36,0 +DA:37,0 +DA:38,0 +DA:40,0 +DA:41,0 +DA:42,0 +DA:43,0 +DA:44,0 +DA:45,0 +DA:46,0 +DA:48,0 +DA:49,0 +DA:52,1 +DA:53,0 +DA:56,1 +LF:40 +LH:16 +end_of_record diff --git a/tests/various/lcov.v b/tests/various/lcov.v new file mode 100644 index 000000000..09fccf70f --- /dev/null +++ b/tests/various/lcov.v @@ -0,0 +1,59 @@ +module top ( + input wire clk, + input wire rst, + input wire [7:0] a, + input wire [7:0] b, + input wire [3:0] c, + input wire en, + output wire [7:0] out1, + output wire [7:0] out2 +); + + // Shared intermediate signal + wire [7:0] ab_sum; + assign ab_sum = a + b; + + // Logic cone for out1 + wire [7:0] cone1_1, cone1_2; + assign cone1_1 = ab_sum ^ {4{c[1:0]}}; + assign cone1_2 = (a & b) | {4{c[3:2]}}; + + reg [7:0] reg1, reg2; // only reg1 feeds into out1, but both share a source location + always @(posedge clk or posedge rst) begin + if (rst) begin + reg1 <= 8'h00; + reg2 <= 8'hFF; + end else if (en) begin + reg1 <= cone1_1 + cone1_2; + reg2 <= cone1_2 - cone1_1; + end + end + + wire [7:0] cone1_3; + assign cone1_3 = reg1 & ~a[0]; + + // Logic cone for out2 + wire [7:0] cone2_1, cone2_2; + assign cone2_1 = (ab_sum << 1) | (a >> 2); + assign cone2_2 = (b ^ {4{c[2:0]}}) & 8'hAA; + + reg [7:0] reg3; + always @(posedge clk or posedge rst) begin + if (rst) + reg3 <= 8'h0F; + else + reg3 <= cone2_1 ^ cone2_2 ^ reg1[7:0]; + end + + wire [7:0] cone2_3; + assign cone2_3 = reg3 | (reg2 ^ 8'h55); + + // Outputs + assign out1 = cone1_3 | (reg1 ^ 8'hA5); + assign out2 = cone2_3 & (reg3 | 8'h5A); + + always @(posedge clk) begin + assert (out1 == 8'h42); + end + +endmodule diff --git a/tests/various/lcov.ys b/tests/various/lcov.ys new file mode 100644 index 000000000..8122611c0 --- /dev/null +++ b/tests/various/lcov.ys @@ -0,0 +1,8 @@ +read_verilog -formal lcov.v +prep -top top +async2sync +chformal -lower +select -set covered t:$assert %ci* +select -set irrelevant o:* %ci* %n +linecoverage -lcov lcov.out @covered @irrelevant %u +exec -expect-return 0 -- diff -q lcov.out lcov.gold diff --git a/tests/various/rename_unescape.ys b/tests/various/rename_unescape.ys new file mode 100644 index 000000000..546d97357 --- /dev/null +++ b/tests/various/rename_unescape.ys @@ -0,0 +1,41 @@ +read_verilog <