mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-03 22:43:57 +00:00
Code Activity

Gowin. Renaming inputs of the DCS primitive.

Browse source 
The dynamic clock selection (DCS) primitive has undergone changes with
the release of the GW5A series—the CLK0,1,2,3 inputs are now
CLKIN0,1,2,3, but only for GW5A series chips.

There are no functional changes, only renaming.

Here we are transferring the description of the DCS primitive from
general to specialized files for each chip series.

We have also fixed a bug in the generation script that caused the loss
of primitive parameters. Fortunately, this only affected the
analog-to-digital converter, which has not yet been implemented.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit 2025-09-20 11:01:25 +10:00 • committed by Lofty
parent 1fa5ceee8c
commit d60dc93e92
5 changed files with 105 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

8
techlibs/gowin/cells_sim.v
View file

@ -1958,14 +1958,6 @@ parameter FREQ_DIV = 100;
parameter REGULATOR_EN = 1'b0;
endmodule
(* blackbox *)
module DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
endmodule
(* blackbox *)
module EMCU (
input FCLK,