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Merge pull request #5550 from YosysHQ/nak/dont_merge_properties

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N. Engelhardt 2025-12-22 16:54:43 +01:00 • committed by GitHub
commit d5b38af4a7
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4 changed files with 26 additions and 1 deletions
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1
frontends/ast/genrtlil.cc
View file

@ -844,6 +844,7 @@ struct AST_INTERNAL::ProcessGenerator
RTLIL::Cell *cell = current_module->addCell(cellname, ID($check)); RTLIL::Cell *cell = current_module->addCell(cellname, ID($check));
set_src_attr(cell, ast); set_src_attr(cell, ast);
cell->set_bool_attribute(ID(keep));
for (auto &attr : ast->attributes) { for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Attribute `%s' with non-constant value!\n", attr.first); log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Attribute `%s' with non-constant value!\n", attr.first);

5
frontends/verific/verificsva.cc
View file

@ -1846,7 +1846,10 @@ struct VerificSvaImporter
if (mode_assume) c = module->addAssume(root_name, sig_a_q, sig_en_q); if (mode_assume) c = module->addAssume(root_name, sig_a_q, sig_en_q);
if (mode_cover) c = module->addCover(root_name, sig_a_q, sig_en_q); if (mode_cover) c = module->addCover(root_name, sig_a_q, sig_en_q);
if (c) importer->import_attributes(c->attributes, root); if (c) {
c->set_bool_attribute(ID(keep));
importer->import_attributes(c->attributes, root);
}
} }
} }
catch (ParserErrorException) catch (ParserErrorException)

5
passes/opt/opt_merge.cc
View file

@ -227,6 +227,11 @@ struct OptMergeWorker
ct.cell_types.erase(ID($anyconst)); ct.cell_types.erase(ID($anyconst));
ct.cell_types.erase(ID($allseq)); ct.cell_types.erase(ID($allseq));
ct.cell_types.erase(ID($allconst)); ct.cell_types.erase(ID($allconst));
ct.cell_types.erase(ID($check));
ct.cell_types.erase(ID($assert));
ct.cell_types.erase(ID($assume));
ct.cell_types.erase(ID($live));
ct.cell_types.erase(ID($cover));
log("Finding identical cells in module `%s'.\n", module->name); log("Finding identical cells in module `%s'.\n", module->name);
assign_map.set(module); assign_map.set(module);

16
tests/opt/opt_merge_properties.ys Normal file
View file

@ -0,0 +1,16 @@
read_verilog -sv <<EOF
module top ();
always_comb begin
label1: cover(0);
label2: cover(0);
end
endmodule
EOF
hierarchy -top top
proc
chformal -lower
clean
opt_merge
select -assert-count 2 t:$cover