mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

Added $tribuf and $_TBUF_ sim models

Browse source
This commit is contained in:
Clifford Wolf 2015-08-16 13:05:32 +02:00
parent 9c33172ece
commit d5b1a90b33
2 changed files with 20 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
techlibs/common/simcells.v
View file

@ -132,6 +132,12 @@ output Y;
assign Y = ~((A | B) & (C | D)); assign Y = ~((A | B) & (C | D));
endmodule endmodule
module \$_TBUF_ (A, E, Y);
input A, E;
output Y;
assign Y = E ? A : 1'bz;
endmodule
module \$_SR_NN_ (S, R, Q); module \$_SR_NN_ (S, R, Q);
input S, R; input S, R;
output reg Q; output reg Q;

14
techlibs/common/simlib.v
View file

@ -1156,6 +1156,20 @@ endmodule
`endif `endif
// -------------------------------------------------------- // --------------------------------------------------------
module \$tribuf (A, EN, Y);
parameter WIDTH = 0;
input [WIDTH-1:0] A;
input EN;
output [WIDTH-1:0] Y;
assign Y = EN ? A : 'bz;
endmodule
// --------------------------------------------------------
module \$assert (A, EN); module \$assert (A, EN);
input A, EN; input A, EN;