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Code Activity

Basic test for checking correct synthesis of SystemVerilog interfaces

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This commit is contained in:
Ruben Undheim 2018-10-18 21:27:04 +02:00
parent a25f370191
commit d5aac2650f
6 changed files with 248 additions and 9 deletions
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41
tests/svinterfaces/runone.sh Executable file
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@ -0,0 +1,41 @@
#!/bin/bash
TESTNAME=$1
STDOUTFILE=${TESTNAME}.log_stdout
STDERRFILE=${TESTNAME}.log_stderr
echo "" > $STDOUTFILE
echo "" > $STDERRFILE
echo -n "Test: ${TESTNAME} -> "
$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE
$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE
rm -f a.out reference_result.txt dut_result.txt
set -e
iverilog -g2012 ${TESTNAME}_syn.v
iverilog -g2012 ${TESTNAME}_ref_syn.v
set +e
iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v
./a.out
mv output.txt reference_result.txt
iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
./a.out
mv output.txt dut_result.txt
diff reference_result.txt dut_result.txt > ${TESTNAME}.diff
RET=$?
if [ "$RET" != "0" ] ; then
echo "ERROR!"
exit -1
fi
echo "ok"
exit 0