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Basic test for checking correct synthesis of SystemVerilog interfaces

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This commit is contained in:
Ruben Undheim 2018-10-18 21:27:04 +02:00
parent a25f370191
commit d5aac2650f
6 changed files with 248 additions and 9 deletions
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tests/svinterfaces/run-test.sh Executable file
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#/bin/bash -e
./runone.sh svinterface1