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Remove init* from xaiger, also topo-sort cells for box flow

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This commit is contained in:
Eddie Hung 2019-04-17 11:08:42 -07:00
parent 116176e151
commit d59185f1d6
1 changed files with 155 additions and 93 deletions
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218
backends/aiger/xaiger.cc
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@ -20,6 +20,8 @@
#include "kernel/yosys.h" #include "kernel/yosys.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/celltypes.h"
#include "kernel/utils.h"
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
@ -46,9 +48,8 @@ struct XAigerWriter
pool<SigBit> input_bits, output_bits; pool<SigBit> input_bits, output_bits;
dict<SigBit, SigBit> not_map, ff_map, alias_map; dict<SigBit, SigBit> not_map, ff_map, alias_map;
dict<SigBit, pair<SigBit, SigBit>> and_map; dict<SigBit, pair<SigBit, SigBit>> and_map;
pool<SigBit> initstate_bits; //pool<SigBit> initstate_bits;
vector<std::pair<SigBit,int>> ci_bits, co_bits; vector<std::pair<SigBit,int>> ci_bits, co_bits;
dict<IdString, unsigned> type_map;
vector<pair<int, int>> aig_gates; vector<pair<int, int>> aig_gates;
vector<int> aig_latchin, aig_latchinit, aig_outputs; vector<int> aig_latchin, aig_latchinit, aig_outputs;
@ -58,11 +59,11 @@ struct XAigerWriter
dict<SigBit, int> ordered_outputs; dict<SigBit, int> ordered_outputs;
dict<SigBit, int> ordered_latches; dict<SigBit, int> ordered_latches;
dict<SigBit, int> init_inputs;
int initstate_ff = 0;
vector<Cell*> box_list; vector<Cell*> box_list;
//dict<SigBit, int> init_inputs;
//int initstate_ff = 0;
int mkgate(int a0, int a1) int mkgate(int a0, int a1)
{ {
aig_m++, aig_a++; aig_m++, aig_a++;
@ -76,10 +77,10 @@ struct XAigerWriter
{ {
aig_map[bit] = -1; aig_map[bit] = -1;
if (initstate_bits.count(bit)) { //if (initstate_bits.count(bit)) {
log_assert(initstate_ff > 0); // log_assert(initstate_ff > 0);
aig_map[bit] = initstate_ff; // aig_map[bit] = initstate_ff;
} else //} else
if (not_map.count(bit)) { if (not_map.count(bit)) {
int a = bit2aig(not_map.at(bit)) ^ 1; int a = bit2aig(not_map.at(bit)) ^ 1;
aig_map[bit] = a; aig_map[bit] = a;
@ -170,8 +171,35 @@ struct XAigerWriter
if (!bit.wire->port_input) if (!bit.wire->port_input)
unused_bits.erase(bit); unused_bits.erase(bit);
dict<SigBit, pool<IdString>> bit_drivers, bit_users;
TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
bool abc_box_seen = false;
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
toposort.node(cell->name);
for (const auto &conn : cell->connections())
{
// HACK!!!
if (cell->type.in("\\SB_DFF", "\\SB_DFFE", "\\SB_DFFESR", "\\SB_DFFSR", "\\SB_DFFESS") && conn.first.in("\\Q"))
continue;
if (yosys_celltypes.cell_known(cell->type)) {
if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
continue;
if (cell->type == "$memrd" && conn.first == "\\DATA")
continue;
}
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
bit_users[bit].insert(cell->name);
if (cell->output(conn.first))
for (auto bit : sigmap(conn.second))
bit_drivers[bit].insert(cell->name);
}
if (cell->type == "$_NOT_") if (cell->type == "$_NOT_")
{ {
SigBit A = sigmap(cell->getPort("\\A").as_bit()); SigBit A = sigmap(cell->getPort("\\A").as_bit());
@ -204,16 +232,63 @@ struct XAigerWriter
continue; continue;
} }
if (cell->type == "$initstate") //if (cell->type == "$initstate")
{ //{
SigBit Y = sigmap(cell->getPort("\\Y").as_bit()); // SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
undriven_bits.erase(Y); // undriven_bits.erase(Y);
initstate_bits.insert(Y); // initstate_bits.insert(Y);
continue; // continue;
} //}
RTLIL::Module* box_module = module->design->module(cell->type); RTLIL::Module* box_module = module->design->module(cell->type);
bool abc_box = box_module && box_module->attributes.count("\\abc_box_id"); if (!box_module || !box_module->attributes.count("\\abc_box_id")) {
for (const auto &c : cell->connections()) {
/*if (c.second.is_fully_const()) continue;*/
for (auto b : c.second.bits()) {
Wire *w = b.wire;
if (!w) continue;
auto is_input = cell->input(c.first);
auto is_output = cell->output(c.first);
log_assert(is_input || is_output);
if (is_input) {
if (!w->port_input) {
SigBit I = sigmap(b);
if (I != b)
alias_map[b] = I;
output_bits.insert(b);
unused_bits.erase(b);
}
}
if (is_output) {
SigBit O = sigmap(b);
input_bits.insert(O);
if (!O.wire->port_output)
undriven_bits.erase(O);
}
}
}
}
else
abc_box_seen = true;
//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
}
if (abc_box_seen) {
for (auto &it : bit_users)
if (bit_drivers.count(it.first))
for (auto driver_cell : bit_drivers.at(it.first))
for (auto user_cell : it.second)
toposort.edge(driver_cell, user_cell);
toposort.sort();
log_assert(!toposort.found_loops);
for (auto cell_name : toposort.sorted) {
RTLIL::Cell *cell = module->cell(cell_name);
RTLIL::Module* box_module = module->design->module(cell->type);
if (!box_module || !box_module->attributes.count("\\abc_box_id"))
continue;
cell->connections_.sort(RTLIL::sort_by_id_str()); cell->connections_.sort(RTLIL::sort_by_id_str());
for (const auto &c : cell->connections()) { for (const auto &c : cell->connections()) {
@ -228,34 +303,21 @@ struct XAigerWriter
if (I != b) if (I != b)
alias_map[b] = I; alias_map[b] = I;
/*if (!output_bits.count(b))*/ /*if (!output_bits.count(b))*/
if (abc_box)
co_bits.emplace_back(b, 0); co_bits.emplace_back(b, 0);
else if (b.wire) {
output_bits.insert(b);
if (!b.wire->port_input)
unused_bits.erase(b);
}
} }
} }
if (is_output) { if (is_output) {
SigBit O = sigmap(b); SigBit O = sigmap(b);
/*if (!input_bits.count(O))*/ /*if (!input_bits.count(O))*/
if (abc_box)
ci_bits.emplace_back(O, 0); ci_bits.emplace_back(O, 0);
else {
input_bits.insert(O);
if (!O.wire->port_output)
undriven_bits.erase(O);
} }
} }
} }
if (!type_map.count(cell->type))
type_map[cell->type] = type_map.size()+1;
}
if (abc_box)
box_list.emplace_back(cell); box_list.emplace_back(cell);
//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell)); }
// TODO: Free memory from toposort, bit_drivers, bit_users
} }
for (auto bit : input_bits) { for (auto bit : input_bits) {
@ -329,15 +391,15 @@ struct XAigerWriter
aig_m++, aig_i++; aig_m++, aig_i++;
} }
if (zinit_mode) //if (zinit_mode)
{ //{
for (auto it : ff_map) { // for (auto it : ff_map) {
if (init_map.count(it.first)) // if (init_map.count(it.first))
continue; // continue;
aig_m++, aig_i++; // aig_m++, aig_i++;
init_inputs[it.first] = 2*aig_m; // init_inputs[it.first] = 2*aig_m;
} // }
} //}
for (auto it : ff_map) { for (auto it : ff_map) {
aig_m++, aig_l++; aig_m++, aig_l++;
@ -349,29 +411,29 @@ struct XAigerWriter
aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0); aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
} }
if (!initstate_bits.empty() || !init_inputs.empty()) { //if (!initstate_bits.empty() || !init_inputs.empty()) {
aig_m++, aig_l++; // aig_m++, aig_l++;
initstate_ff = 2*aig_m+1; // initstate_ff = 2*aig_m+1;
aig_latchinit.push_back(0); // aig_latchinit.push_back(0);
} //}
if (zinit_mode) //if (zinit_mode)
{ //{
for (auto it : ff_map) // for (auto it : ff_map)
{ // {
int l = ordered_latches[it.first]; // int l = ordered_latches[it.first];
if (aig_latchinit.at(l) == 1) // if (aig_latchinit.at(l) == 1)
aig_map[it.first] ^= 1; // aig_map[it.first] ^= 1;
if (aig_latchinit.at(l) == 2) // if (aig_latchinit.at(l) == 2)
{ // {
int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1); // int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
int gated_initin = mkgate(init_inputs[it.first], initstate_ff); // int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1; // aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
} // }
} // }
} //}
for (auto it : ff_map) { for (auto it : ff_map) {
int a = bit2aig(it.second); int a = bit2aig(it.second);
@ -382,8 +444,8 @@ struct XAigerWriter
aig_latchin.push_back(a); aig_latchin.push_back(a);
} }
if (!initstate_bits.empty() || !init_inputs.empty()) //if (!initstate_bits.empty() || !init_inputs.empty())
aig_latchin.push_back(1); // aig_latchin.push_back(1);
for (auto &c : co_bits) { for (auto &c : co_bits) {
RTLIL::SigBit bit = c.first; RTLIL::SigBit bit = c.first;
@ -518,14 +580,14 @@ struct XAigerWriter
symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire))); symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
} }
if (init_inputs.count(sig[i])) { //if (init_inputs.count(sig[i])) {
int a = init_inputs.at(sig[i]); // int a = init_inputs.at(sig[i]);
log_assert((a & 1) == 0); // log_assert((a & 1) == 0);
if (GetSize(wire) != 1) // if (GetSize(wire) != 1)
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i)); // symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
else // else
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire))); // symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
} //}
if (ordered_latches.count(sig[i])) { if (ordered_latches.count(sig[i])) {
int l = ordered_latches.at(sig[i]); int l = ordered_latches.at(sig[i]);
@ -687,12 +749,12 @@ struct XAigerWriter
continue; continue;
} }
if (init_inputs.count(sig[i])) { //if (init_inputs.count(sig[i])) {
int a = init_inputs.at(sig[i]); // int a = init_inputs.at(sig[i]);
log_assert((a & 1) == 0); // log_assert((a & 1) == 0);
init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire)); // init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
continue; // continue;
} //}
if (ordered_latches.count(sig[i])) { if (ordered_latches.count(sig[i])) {
int l = ordered_latches.at(sig[i]); int l = ordered_latches.at(sig[i]);