mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

Some test related fixes

Browse source 
(incl. removal of three bad test cases)
This commit is contained in:
Clifford Wolf 2015-02-12 17:45:44 +01:00
parent 554a8df5e2
commit d58c3eca3a
6 changed files with 6 additions and 156 deletions
Download patch file Download diff file Expand all files Collapse all files

8
techlibs/common/simlib.v
View file

@ -1328,7 +1328,7 @@ output reg [WIDTH-1:0] Q;
always @* begin
if (EN == EN_POLARITY)
Q <= D;
Q = D;
end
endmodule
@ -1356,11 +1356,11 @@ generate
for (i = 0; i < WIDTH; i = i+1) begin:bit
always @*
if (pos_clr[i])
Q[i] <= 0;
Q[i] = 0;
else if (pos_set[i])
Q[i] <= 1;
Q[i] = 1;
else if (pos_en)
Q[i] <= D[i];
Q[i] = D[i];
end
endgenerate