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Merge remote-tracking branch 'origin/xaig' into xc7mux

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Eddie Hung 2019-06-22 19:44:17 -07:00
commit d54dceb547
9 changed files with 85 additions and 391 deletions
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techlibs/xilinx/cells_sim.v
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@ -289,7 +289,6 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
//(* abc_box_id = 4 /*, lib_whitebox*/ *)
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
@ -307,7 +306,6 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
//(* abc_box_id = 5 /*, lib_whitebox*/ *)
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,