From d525a414978236682e067180a8a5d94189f67335 Mon Sep 17 00:00:00 2001
From: Ethan Mahintorabi <ethanmoon@google.com>
Date: Tue, 15 Aug 2023 20:03:46 +0000
Subject: [PATCH] abc: Exposes dont_use flag in ABC
ABC's read_lib command has a dont_use
cell list that is configurable by the user.
This PR exposes that option to Yosys.
See
https://github.com/berkeley-abc/abc/blob/5405d4787a86615de76afccf1356676fb5c56c1c/src/map/scl/scl.c#L285
for documentation on this option.
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
---
passes/techmap/abc.cc | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 364a8e544..f36cadc88 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -702,7 +702,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
std::vector<std::string> &liberty_files, std::vector<std::string> &genlib_files, std::string constr_file,
bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target,
std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
- const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress)
+ const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress, std::vector<std::string> &dont_use_cells)
{
module = current_module;
map_autoidx = autoidx++;
@@ -795,8 +795,13 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name.c_str());
if (!liberty_files.empty() || !genlib_files.empty()) {
- for (std::string liberty_file : liberty_files)
- abc_script += stringf("read_lib -w \"%s\"; ", liberty_file.c_str());
+ std::string dont_use_args;
+ for (std::string dont_use_cell : dont_use_cells) {
+ dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str());
+ }
+ for (std::string liberty_file : liberty_files) {
+ abc_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args.c_str(), liberty_file.c_str());
+ }
for (std::string liberty_file : genlib_files)
abc_script += stringf("read_library \"%s\"; ", liberty_file.c_str());
if (!constr_file.empty())
@@ -1503,6 +1508,10 @@ struct AbcPass : public Pass {
log(" generate netlists for the specified cell library (using the liberty\n");
log(" file format).\n");
log("\n");
+ log(" -dont_use <cell_name>\n");
+ log(" generate netlists for the specified cell library (using the liberty\n");
+ log(" file format).\n");
+ log("\n");
log(" -genlib <file>\n");
log(" generate netlists for the specified cell library (using the SIS Genlib\n");
log(" file format).\n");
@@ -1639,7 +1648,7 @@ struct AbcPass : public Pass {
std::string exe_file = yosys_abc_executable;
std::string script_file, default_liberty_file, constr_file, clk_str;
- std::vector<std::string> liberty_files, genlib_files;
+ std::vector<std::string> liberty_files, genlib_files, dont_use_cells;
std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
bool show_tempdir = false, sop_mode = false;
@@ -1722,6 +1731,10 @@ struct AbcPass : public Pass {
liberty_files.push_back(args[++argidx]);
continue;
}
+ if (arg == "-dont_use" && argidx+1 < args.size()) {
+ dont_use_cells.push_back(args[++argidx]);
+ continue;
+ }
if (arg == "-genlib" && argidx+1 < args.size()) {
genlib_files.push_back(args[++argidx]);
continue;
@@ -2028,7 +2041,7 @@ struct AbcPass : public Pass {
if (!dff_mode || !clk_str.empty()) {
abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
- delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress);
+ delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress, dont_use_cells);
continue;
}
@@ -2190,7 +2203,7 @@ struct AbcPass : public Pass {
srst_polarity = std::get<6>(it.first);
srst_sig = assign_map(std::get<7>(it.first));
abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
- keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress);
+ keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress, dont_use_cells);
assign_map.set(mod);
}
}