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This commit is contained in:
Miodrag Milanovic 2019-08-09 12:37:10 +02:00
parent 7a860c5623
commit d51b135e33

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@ -31,7 +31,7 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
output [Y_WIDTH-1:0] X, Y; output [Y_WIDTH-1:0] X, Y;
input CI, BI; input CI, BI;
output CO; output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
@ -41,38 +41,36 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH:0] C;
wire [Y_WIDTH+2:0] C = {COx, CI};
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_cin ( adder_cin (
.I0(C[0]), .I0(CI),
.I1(1'b1), .I1(1'b1),
.CI(1'b0), .CI(1'b0),
.CO(COx[0]) .CO(C[0])
); );
genvar i; genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_i ( adder_i (
.I0(AA[i]), .I0(AA[i]),
.I1(BB[i]), .I1(BB[i]),
.CI(C[i+1]), .CI(C[i]),
.O(Y[i]), .O(Y[i]),
.CO(COx[i+1]) .CO(C[i+1])
); );
end: slice EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_cout (
.I0(1'b0),
.I1(1'b0),
.CI(C[i+1]),
.O(CO[i])
);
end: slice
endgenerate endgenerate
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) /* End implementation */
adder_cout ( assign X = AA ^ BB;
.I0(1'b0),
.I1(1'b0),
.CI(C[Y_WIDTH+1]),
.O(COx[Y_WIDTH+1])
);
assign CO = COx[Y_WIDTH+1];
/* End implementation */
assign X = AA ^ BB;
endmodule endmodule