mirror of
https://github.com/YosysHQ/yosys
synced 2025-05-09 16:55:49 +00:00
Merge 4bd91fbb11 into 6378ba10eb
This commit is contained in:
Akash Levy
GitHub
commit
d4ba45aea2
7 changed files with 488 additions and 0 deletions
1
Makefile
1
Makefile
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@ -894,6 +894,7 @@ SH_TEST_DIRS += tests/bram
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SH_TEST_DIRS += tests/svinterfaces
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SH_TEST_DIRS += tests/xprop
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SH_TEST_DIRS += tests/select
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SH_TEST_DIRS += tests/peepopt
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SH_TEST_DIRS += tests/proc
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SH_TEST_DIRS += tests/blif
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SH_TEST_DIRS += tests/arch
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@ -32,6 +32,7 @@ PEEPOPT_PATTERN = passes/opt/peepopt_shiftmul_right.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_shiftmul_left.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_shiftadd.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_muldiv.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_muldiv_c.pmg
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PEEPOPT_PATTERN += passes/opt/peepopt_formal_clockgateff.pmg
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passes/opt/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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@ -29,6 +29,14 @@ bool did_something;
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// scratchpad configurations for pmgen
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int shiftadd_max_ratio;
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// Helper function, removes LSB 0s
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SigSpec remove_bottom_padding(SigSpec sig)
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{
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int i = 0;
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for (; i < sig.size() - 1 && sig[i] == State::S0; i++);
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return sig.extract(i, sig.size() - i);
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}
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#include "passes/opt/peepopt_pm.h"
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struct PeepoptPass : public Pass {
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@ -45,6 +53,8 @@ struct PeepoptPass : public Pass {
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log("\n");
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log(" * muldiv - Replace (A*B)/B with A\n");
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log("\n");
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log(" * muldiv_c - Replace (A*B)/C with A*(B/C) when C is a const divisible by B.\n");
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log("\n");
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log(" * shiftmul - Replace A>>(B*C) with A'>>(B<<K) where C and K are constants\n");
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log(" and A' is derived from A by appropriately inserting padding\n");
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log(" into the signal. (right variant)\n");
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@ -106,6 +116,7 @@ struct PeepoptPass : public Pass {
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pm.run_shiftmul_right();
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pm.run_shiftmul_left();
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pm.run_muldiv();
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pm.run_muldiv_c();
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}
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}
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}
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125
passes/opt/peepopt_muldiv_c.pmg
Normal file
125
passes/opt/peepopt_muldiv_c.pmg
Normal file
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@ -0,0 +1,125 @@
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pattern muldiv_c
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//
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// Authored by Akash Levy and Alain Dargelas of Silimate, Inc. under ISC license.
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// Transforms mul->div into const->mul when b and c are divisible constants:
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// y = (a * b_const) / c_const ===> a * eval(b_const / c_const)
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//
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state <SigSpec> a b_const mul_y
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match mul
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// Select multiplier
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select mul->type == $mul
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endmatch
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code a b_const mul_y
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// Get multiplier signals
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a = port(mul, \A);
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b_const = port(mul, \B);
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mul_y = port(mul, \Y);
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// Fanout of each multiplier Y bit should be 1 (no bit-split)
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if (nusers(mul_y) != 2)
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reject;
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// A and B can be interchanged
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branch;
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std::swap(a, b_const);
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endcode
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match div
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// Select div of form (a * b_const) / c_const
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select div->type == $div
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// Check that b_const and c_const is constant
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filter b_const.is_fully_const()
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filter port(div, \B).is_fully_const()
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index <SigSpec> remove_bottom_padding(port(div, \A)) === mul_y
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endmatch
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code
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// Get div signals
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SigSpec div_a = port(div, \A);
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SigSpec c_const = port(div, \B);
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SigSpec div_y = port(div, \Y);
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// Get offset of multiplier result chunk in divider
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int offset = GetSize(div_a) - GetSize(mul_y);
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// Get properties and values of b_const and c_const
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// b_const may be coming from the A port
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// But it is an RTLIL invariant that A_SIGNED equals B_SIGNED
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bool b_const_signed = mul->getParam(ID::B_SIGNED).as_bool();
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bool c_const_signed = div->getParam(ID::B_SIGNED).as_bool();
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int b_const_int = b_const.as_int(b_const_signed);
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int c_const_int = c_const.as_int(c_const_signed);
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int b_const_int_shifted = b_const_int << offset;
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// Helper lambdas for two's complement math
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auto sign2sComplement = [](auto value, int numBits) {
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if (value & (1 << (numBits - 1))) {
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return -1;
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} else {
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return 1;
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}
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};
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auto twosComplement = [](auto value, int numBits) {
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if (value & (1 << (numBits - 1))) {
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return (~value) + 1; // invert bits before adding 1
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} else {
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return value;
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}
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};
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// Two's complement conversion
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if (b_const_signed)
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b_const_int = sign2sComplement(b_const_int, GetSize(b_const)) * twosComplement(b_const_int, GetSize(b_const));
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if (c_const_signed)
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c_const_int = sign2sComplement(c_const_int, GetSize(c_const)) * twosComplement(c_const_int, GetSize(c_const));
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// Calculate the constant and compress the width to fit the value
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Const const_ratio;
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Const b_const_actual;
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// Avoid division by zero
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if (c_const_int == 0)
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reject;
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b_const_actual = b_const_int_shifted;
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b_const_actual.compress(b_const_signed);
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const_ratio = b_const_int_shifted / c_const_int;
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const_ratio.compress(b_const_signed | c_const_signed);
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// Integer values should be lesser than 32 bits
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// This is because we are using C++ types, and int is 32 bits
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// FIXME: use long long or BigInteger to make pass work with >32 bits
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if (GetSize(mul->getParam(ID::B_WIDTH)) > 32)
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reject;
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if (GetSize(b_const) > 32)
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reject;
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if (GetSize(c_const) + offset > 32)
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reject;
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// Check for potential multiplier overflow
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if (GetSize(b_const_actual) + GetSize(a) > GetSize(mul_y))
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reject;
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// Check that there are only zeros before offset
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if (offset < 0 || !div_a.extract(0, offset).is_fully_zero())
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reject;
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// Check that b is divisible by c
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if (b_const_int_shifted % c_const_int != 0)
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reject;
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// Rewire to only keep multiplier
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mul->setPort(\A, a);
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mul->setPort(\B, const_ratio);
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mul->setPort(\Y, div_y);
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// Remove divider
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autoremove(div);
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// Log, fixup, accept
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log("muldiv_const pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
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mul->fixup_parameters();
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accept;
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endcode
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1
tests/peepopt/.gitignore
vendored
Normal file
1
tests/peepopt/.gitignore
vendored
Normal file
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@ -0,0 +1 @@
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/*.log
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343
tests/peepopt/muldiv_c.ys
Normal file
343
tests/peepopt/muldiv_c.ys
Normal file
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@ -0,0 +1,343 @@
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log -header "Test simple positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [11:0] a,
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output wire [11:0] y
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);
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assign y = (a * 16'd5140) / (257 * 2);
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endmodule
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EOF
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-none t:$div
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design -reset
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log -pop
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log -header "Test negative case where div is kept"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire signed [11:0] a,
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output wire signed [31:0] y,
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output wire probe
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);
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wire [28:0] tmp = (a * 16'd5140);
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assign probe = tmp[28];
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assign y = tmp[27:0] / (257 * 2);
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endmodule
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EOF
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-any t:$div
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design -reset
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log -pop
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log -header "Basic pattern transformed: (a * b) / c"
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log -push
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read_verilog <<EOT
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module top(
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input signed [3:0] a,
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output signed [7:0] y,
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);
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wire signed [7:0] mul;
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assign mul = a * 4'sd6;
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assign y = mul / 8'sd3;
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endmodule
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EOT
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$div
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design -reset
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log -pop
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log -header "Transformed on symmetry in multiplication"
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log -push
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read_verilog <<EOT
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module top(
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input signed [3:0] a,
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output signed [7:0] y,
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);
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wire signed [7:0] mul;
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assign mul = 4'sd6 * a;
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assign y = mul / 8'sd3;
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endmodule
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EOT
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$div
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design -reset
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log -pop
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log -header "Transformed on b == c"
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log -push
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read_verilog <<EOT
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module top(
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input signed [3:0] a,
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output signed [7:0] y,
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);
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wire signed [7:0] mul;
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assign mul = a * 4'sd6;
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assign y = mul / 8'sd6;
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endmodule
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EOT
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$div
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design -reset
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log -pop
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log -header "b negative, c positive"
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log -push
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read_verilog <<EOT
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module top(
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input signed [3:0] a,
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output signed [7:0] y,
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);
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wire signed [7:0] mul;
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assign mul = a * -4'sd6;
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assign y = mul / 8'sd3;
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endmodule
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EOT
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$div
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design -reset
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log -pop
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log -header "b positive, c negative"
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log -push
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read_verilog <<EOT
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module top(
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input signed [3:0] a,
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output signed [7:0] y,
|
||||
);
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wire signed [7:0] mul;
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assign mul = a * 4'sd6;
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assign y = mul / -8'sd3;
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endmodule
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EOT
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equiv_opt -assert peepopt
|
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design -load postopt
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$div
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design -reset
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|
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log -pop
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log -header "No transform when b not divisible by c"
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log -push
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read_verilog <<EOT
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module top(
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input signed [3:0] a,
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output signed [7:0] y,
|
||||
);
|
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wire signed [7:0] mul;
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assign mul = a * 4'sd3;
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assign y = mul / 8'sd2;
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endmodule
|
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EOT
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mul
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select -assert-count 1 t:$div
|
||||
design -reset
|
||||
|
||||
|
||||
log -pop
|
||||
log -header "No transform when product has a second fanout"
|
||||
log -push
|
||||
read_verilog <<EOT
|
||||
module top(
|
||||
input signed [3:0] a,
|
||||
output signed [7:0] y,
|
||||
output signed [7:0] z,
|
||||
);
|
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wire signed [7:0] mul;
|
||||
assign mul = a * 4'sd6;
|
||||
assign y = mul / 8'sd3;
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assign z = mul;
|
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endmodule
|
||||
EOT
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mul
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||||
select -assert-count 1 t:$div
|
||||
design -reset
|
||||
|
||||
|
||||
log -pop
|
||||
log -header "No transform when divisor is 0"
|
||||
log -push
|
||||
read_verilog <<EOT
|
||||
module top(
|
||||
input signed [3:0] a,
|
||||
output signed [7:0] y,
|
||||
);
|
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wire signed [7:0] mul;
|
||||
assign mul = a * 4'sd4;
|
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assign y = mul / 8'sd0;
|
||||
endmodule
|
||||
EOT
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mul
|
||||
select -assert-count 1 t:$div
|
||||
design -reset
|
||||
|
||||
|
||||
log -pop
|
||||
log -header "No transform when (a*b) output can overflow (divider’s A input signed)"
|
||||
log -push
|
||||
read_verilog <<EOT
|
||||
module top(
|
||||
input signed [3:0] a,
|
||||
output signed [7:0] y,
|
||||
);
|
||||
wire signed [5:0] mul;
|
||||
assign mul = a * 4'sd6;
|
||||
assign y = mul / 8'sd3;
|
||||
endmodule
|
||||
EOT
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mul
|
||||
select -assert-count 1 t:$div
|
||||
design -reset
|
||||
|
||||
|
||||
log -pop
|
||||
log -header "No transform when (a*b) output can overflow (divider’s A input signed)"
|
||||
log -push
|
||||
read_verilog <<EOT
|
||||
module top(
|
||||
input signed [3:0] a,
|
||||
output signed [7:0] y,
|
||||
);
|
||||
wire signed [6:0] mul;
|
||||
assign mul = a * 4'sd6;
|
||||
assign y = mul / 8'sd3;
|
||||
endmodule
|
||||
EOT
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mul
|
||||
select -assert-count 1 t:$div
|
||||
design -reset
|
||||
|
||||
|
||||
log -pop
|
||||
log -header "No transform when (a*b) output can overflow (divider’s A input unsigned)"
|
||||
log -push
|
||||
read_verilog <<EOT
|
||||
module top(
|
||||
input [3:0] a,
|
||||
output [7:0] y,
|
||||
);
|
||||
wire [4:0] mul;
|
||||
assign mul = a * 4'd4;
|
||||
assign y = mul / 8'd2;
|
||||
endmodule
|
||||
EOT
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mul
|
||||
select -assert-count 1 t:$div
|
||||
design -reset
|
||||
|
||||
log -pop
|
||||
log -header "No transform when (a*b) output can overflow (divider’s A input unsigned)"
|
||||
log -push
|
||||
read_verilog <<EOT
|
||||
module top(
|
||||
input [3:0] a,
|
||||
output [7:0] y,
|
||||
);
|
||||
wire [6:0] mul;
|
||||
assign mul = a * 4'd8;
|
||||
assign y = mul / 8'd2;
|
||||
endmodule
|
||||
EOT
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mul
|
||||
select -assert-count 1 t:$div
|
||||
design -reset
|
||||
|
||||
|
||||
log -pop
|
||||
log -header "No transform when (a*b) and x/c fitting criteria but not connected (x != a*b)"
|
||||
log -push
|
||||
read_verilog <<EOT
|
||||
module top(
|
||||
input signed [3:0] a,
|
||||
input signed [7:0] b,
|
||||
output signed [7:0] y,
|
||||
output signed [7:0] z,
|
||||
);
|
||||
assign y = a * 4'sd6;
|
||||
assign z = b / 8'sd3;
|
||||
endmodule
|
||||
EOT
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mul
|
||||
select -assert-count 1 t:$div
|
||||
design -reset
|
||||
|
||||
log -pop
|
||||
log -header "No transform when b only divisible by c if b misinterpreted as unsigned"
|
||||
# b 1001 is -7 but 9 misinterpreted
|
||||
# c 11 is 3
|
||||
log -push
|
||||
read_verilog <<EOT
|
||||
module top(
|
||||
input signed [3:0] a,
|
||||
output signed [7:0] y,
|
||||
);
|
||||
wire signed [7:0] mul;
|
||||
assign mul = a * 4'sb1001;
|
||||
assign y = mul / 8'sb11;
|
||||
endmodule
|
||||
EOT
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mul
|
||||
select -assert-count 1 t:$div
|
||||
design -reset
|
||||
|
||||
log -pop
|
||||
log -header "Transform even if (a*b) result would overflow if divider’s A input signedness is confused & (A input is unsigned)"
|
||||
log -push
|
||||
# Transform even if:
|
||||
# (a*b) result would overflow if divider’s A input signedness is confused
|
||||
# (A input is unsigned)
|
||||
read_verilog <<EOT
|
||||
module top(
|
||||
input [3:0] a,
|
||||
output [7:0] y,
|
||||
);
|
||||
wire [7:0] mul;
|
||||
assign mul = a * 4'd6;
|
||||
assign y = mul / 8'd3;
|
||||
endmodule
|
||||
EOT
|
||||
equiv_opt -assert peepopt
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$mul
|
||||
select -assert-count 0 t:$div
|
||||
design -reset
|
||||
6
tests/peepopt/run-test.sh
Normal file
6
tests/peepopt/run-test.sh
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
#!/usr/bin/env bash
|
||||
set -e
|
||||
for x in *.ys; do
|
||||
echo "Running $x.."
|
||||
../../yosys -ql ${x%.ys}.log $x
|
||||
done
|
||||
Loading…
Add table
Add a link
Reference in a new issue