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Added support for dlatchsr cells

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This commit is contained in:
Clifford Wolf 2014-03-31 14:14:40 +02:00
parent a3b9692a68
commit d4a1b0af5b
5 changed files with 207 additions and 1 deletions
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32
techlibs/common/simlib.v
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@ -1097,6 +1097,38 @@ endmodule
// --------------------------------------------------------
module \$dlatchsr (EN, SET, CLR, D, Q);
parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
input EN;
input [WIDTH-1:0] SET, CLR, D;
output reg [WIDTH-1:0] Q;
wire pos_en = EN == EN_POLARITY;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bit
always @*
if (pos_clr[i])
Q[i] <= 0;
else if (pos_set[i])
Q[i] <= 1;
else if (pos_en)
Q[i] <= D[i];
end
endgenerate
endmodule
// --------------------------------------------------------
module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);
parameter NAME = "";