mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-14 23:05:28 +00:00
Code Activity

Added support for dlatchsr cells

Browse source
This commit is contained in:
Clifford Wolf 2014-03-31 14:14:40 +02:00
parent a3b9692a68
commit d4a1b0af5b
5 changed files with 207 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

104
techlibs/common/simcells.v
View file

@ -325,3 +325,107 @@ always @* begin
end
endmodule
module \$_DLATCHSR_NNN_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
module \$_DLATCHSR_NNP_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
module \$_DLATCHSR_NPN_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
module \$_DLATCHSR_NPP_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 0)
Q <= D;
end
endmodule
module \$_DLATCHSR_PNN_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
module \$_DLATCHSR_PNP_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
module \$_DLATCHSR_PPN_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule
module \$_DLATCHSR_PPP_ (E, S, R, D, Q);
input E, S, R, D;
output reg Q;
always @* begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else if (E == 1)
Q <= D;
end
endmodule