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Add "verific -L"

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-10-24 09:14:03 +02:00
parent f02623abb5
commit d49c6b2cba
1 changed files with 12 additions and 1 deletions
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13
frontends/verific/verific.cc
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@ -1939,12 +1939,18 @@ struct VerificPass : public Pass {
log("Load the specified VHDL files into Verific.\n"); log("Load the specified VHDL files into Verific.\n");
log("\n"); log("\n");
log("\n"); log("\n");
log(" verific -work <libname> {-sv|-vhdl|...} <hdl-file>\n"); log(" verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
log("\n"); log("\n");
log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n"); log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
log("(default library when -work is not present: \"work\")\n"); log("(default library when -work is not present: \"work\")\n");
log("\n"); log("\n");
log("\n"); log("\n");
log(" verific [-L <libname>] {-sv|-vhdl|...} <hdl-file>\n");
log("\n");
log("Look up external definitions in the specified library.\n");
log("(-L may be used more than once)\n");
log("\n");
log("\n");
log(" verific -vlog-incdir <directory>..\n"); log(" verific -vlog-incdir <directory>..\n");
log("\n"); log("\n");
log("Add Verilog include directories.\n"); log("Add Verilog include directories.\n");
@ -2158,12 +2164,17 @@ struct VerificPass : public Pass {
goto check_error; goto check_error;
} }
veri_file::RemoveAllLOptions();
for (; argidx < GetSize(args); argidx++) for (; argidx < GetSize(args); argidx++)
{ {
if (args[argidx] == "-work" && argidx+1 < GetSize(args)) { if (args[argidx] == "-work" && argidx+1 < GetSize(args)) {
work = args[++argidx]; work = args[++argidx];
continue; continue;
} }
if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
veri_file::AddLOption(args[++argidx].c_str());
continue;
}
break; break;
} }