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Revert "Refactor full_selection"

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Miodrag Milanović 2025-04-07 12:11:55 +02:00 committed by GitHub
parent 98d4355b82
commit d49364d96f
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38 changed files with 270 additions and 707 deletions

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@ -13,5 +13,5 @@ run_subtest value
run_subtest value_fuzz
# Compile-only test.
../../yosys -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"
../../yosys -p "read_verilog test_unconnected_output.v; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"
${CC:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc