mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-11 17:54:44 +00:00
Code Activity

Revert "Refactor full_selection"

Browse source
This commit is contained in:
Miodrag Milanović 2025-04-07 12:11:55 +02:00 • committed by GitHub
parent 98d4355b82
commit d49364d96f
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
38 changed files with 270 additions and 707 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/techmap/clockgate.cc
View file

@ -333,7 +333,7 @@ struct ClockgatePass : public Pass {
dict<ClkNetInfo, GClkNetInfo> clk_nets;
int gated_flop_count = 0;
for (auto module : design->selected_unboxed_whole_modules()) {
for (auto module : design->selected_whole_modules()) {
for (auto cell : module->cells()) {
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
continue;