mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-24 13:18:56 +00:00
Revert "Refactor full_selection"
This commit is contained in:
parent
98d4355b82
commit
d49364d96f
38 changed files with 270 additions and 707 deletions
|
@ -57,7 +57,7 @@ struct CutpointPass : public Pass {
|
|||
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
if (module->is_selected_whole()) {
|
||||
if (design->selected_whole_module(module->name)) {
|
||||
log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
|
||||
module->new_connections(std::vector<RTLIL::SigSig>());
|
||||
for (auto cell : vector<Cell*>(module->cells()))
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue