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Revert "Refactor full_selection"

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Miodrag Milanović 2025-04-07 12:11:55 +02:00 • committed by GitHub
parent 98d4355b82
commit d49364d96f
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GPG key ID: B5690EEEBB952194
38 changed files with 270 additions and 707 deletions
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2
passes/sat/cutpoint.cc
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@ -57,7 +57,7 @@ struct CutpointPass : public Pass {
for (auto module : design->selected_modules())
{
if (module->is_selected_whole()) {
if (design->selected_whole_module(module->name)) {
log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
module->new_connections(std::vector<RTLIL::SigSig>());
for (auto cell : vector<Cell*>(module->cells()))

4
passes/sat/sim.cc
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@ -2887,7 +2887,7 @@ struct SimPass : public Pass {
if (!top_mod)
log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
} else {
auto mods = design->selected_unboxed_whole_modules();
auto mods = design->selected_whole_modules();
if (GetSize(mods) != 1)
log_cmd_error("Only one top module must be selected.\n");
top_mod = mods.front();
@ -3016,7 +3016,7 @@ struct Fst2TbPass : public Pass {
if (!top_mod)
log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
} else {
auto mods = design->selected_unboxed_whole_modules();
auto mods = design->selected_whole_modules();
if (GetSize(mods) != 1)
log_cmd_error("Only one top module must be selected.\n");
top_mod = mods.front();