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Revert "Refactor full_selection"

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Miodrag Milanović 2025-04-07 12:11:55 +02:00 • committed by GitHub
parent 98d4355b82
commit d49364d96f
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38 changed files with 270 additions and 707 deletions
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289
passes/cmds/select.cc
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@ -141,42 +141,24 @@ static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, co
return match_attr(attributes, match_expr, std::string(), 0);
}
static void select_all(RTLIL::Design *design, RTLIL::Selection &lhs)
{
if (!lhs.selects_all())
return;
lhs.current_design = design;
lhs.selected_modules.clear();
for (auto mod : design->modules()) {
if (!lhs.selects_boxes && mod->get_blackbox_attribute())
continue;
lhs.selected_modules.insert(mod->name);
}
lhs.full_selection = false;
lhs.complete_selection = false;
}
static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
{
if (lhs.selects_all()) {
lhs.clear();
if (lhs.full_selection) {
lhs.full_selection = false;
lhs.selected_modules.clear();
lhs.selected_members.clear();
return;
}
if (lhs.selected_modules.size() == 0 && lhs.selected_members.size() == 0) {
if (lhs.selects_boxes)
lhs.complete_selection = true;
else
lhs.full_selection = true;
lhs.full_selection = true;
return;
}
auto new_sel = RTLIL::Selection::EmptySelection();
RTLIL::Selection new_sel(false);
for (auto mod : design->modules())
{
if (!lhs.selects_boxes && mod->get_blackbox_attribute())
continue;
if (lhs.selected_whole_module(mod->name))
continue;
if (!lhs.selected_module(mod->name)) {
@ -230,7 +212,7 @@ static void select_op_random(RTLIL::Design *design, RTLIL::Selection &lhs, int c
}
}
lhs = RTLIL::Selection(false, lhs.selects_boxes, design);
lhs = RTLIL::Selection(false);
while (!objects.empty() && count-- > 0)
{
@ -261,7 +243,7 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection &lhs)
{
RTLIL::Selection new_sel(false, lhs.selects_boxes, design);
RTLIL::Selection new_sel(false);
for (auto mod : design->modules())
if (lhs.selected_module(mod->name))
for (auto cell : mod->cells())
@ -272,7 +254,7 @@ static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection &
static void select_op_module_to_cells(RTLIL::Design *design, RTLIL::Selection &lhs)
{
RTLIL::Selection new_sel(false, lhs.selects_boxes, design);
RTLIL::Selection new_sel(false);
for (auto mod : design->modules())
for (auto cell : mod->cells())
if ((design->module(cell->type) != nullptr) && lhs.selected_whole_module(cell->type))
@ -292,8 +274,6 @@ static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs)
{
for (auto mod : design->modules())
{
if (!lhs.selects_boxes && mod->get_blackbox_attribute())
continue;
if (lhs.selected_whole_module(mod->name))
continue;
if (!lhs.selected_module(mod->name))
@ -312,38 +292,18 @@ static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs)
}
}
static void select_op_union(RTLIL::Design* design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
static void select_op_union(RTLIL::Design*, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
{
if (lhs.complete_selection)
return;
else if (rhs.complete_selection) {
lhs.complete_selection = true;
lhs.optimize(design);
return;
}
if (rhs.selects_boxes) {
if (lhs.full_selection) {
select_all(design, lhs);
}
lhs.selects_boxes = true;
}
else if (lhs.full_selection)
return;
if (rhs.full_selection) {
if (lhs.selects_boxes) {
auto new_rhs = RTLIL::Selection(rhs);
select_all(design, new_rhs);
for (auto mod : new_rhs.selected_modules)
lhs.selected_modules.insert(mod);
} else {
lhs.clear();
lhs.full_selection = true;
}
lhs.full_selection = true;
lhs.selected_modules.clear();
lhs.selected_members.clear();
return;
}
if (lhs.full_selection)
return;
for (auto &it : rhs.selected_members)
for (auto &it2 : it.second)
lhs.selected_members[it.first].insert(it2);
@ -356,30 +316,20 @@ static void select_op_union(RTLIL::Design* design, RTLIL::Selection &lhs, const
static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
{
if (rhs.complete_selection) {
lhs.clear();
return;
}
if (rhs.full_selection) {
if (lhs.selects_boxes) {
auto new_rhs = RTLIL::Selection(rhs);
select_all(design, new_rhs);
select_all(design, lhs);
for (auto mod : new_rhs.selected_modules) {
lhs.selected_modules.erase(mod);
lhs.selected_members.erase(mod);
}
} else {
lhs.clear();
}
lhs.full_selection = false;
lhs.selected_modules.clear();
lhs.selected_members.clear();
return;
}
if (rhs.empty() || lhs.empty())
return;
select_all(design, lhs);
if (lhs.full_selection) {
if (!rhs.full_selection && rhs.selected_modules.size() == 0 && rhs.selected_members.size() == 0)
return;
lhs.full_selection = false;
for (auto mod : design->modules())
lhs.selected_modules.insert(mod->name);
}
for (auto &it : rhs.selected_modules) {
lhs.selected_modules.erase(it);
@ -416,46 +366,38 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R
static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
{
if (rhs.complete_selection)
if (rhs.full_selection)
return;
if (rhs.full_selection && !lhs.selects_boxes)
return;
if (lhs.empty())
return;
if (rhs.empty()) {
lhs.clear();
return;
if (lhs.full_selection) {
lhs.full_selection = false;
for (auto mod : design->modules())
lhs.selected_modules.insert(mod->name);
}
select_all(design, lhs);
std::vector<RTLIL::IdString> del_list;
for (auto mod_name : lhs.selected_modules) {
if (rhs.selected_whole_module(mod_name))
continue;
if (rhs.selected_module(mod_name))
for (auto memb_name : rhs.selected_members.at(mod_name))
lhs.selected_members[mod_name].insert(memb_name);
del_list.push_back(mod_name);
}
for (auto &it : lhs.selected_modules)
if (rhs.selected_modules.count(it) == 0) {
if (rhs.selected_members.count(it) > 0)
for (auto &it2 : rhs.selected_members.at(it))
lhs.selected_members[it].insert(it2);
del_list.push_back(it);
}
for (auto &it : del_list)
lhs.selected_modules.erase(it);
del_list.clear();
for (auto &it : lhs.selected_members) {
if (rhs.selected_whole_module(it.first))
if (rhs.selected_modules.count(it.first) > 0)
continue;
if (!rhs.selected_module(it.first)) {
if (rhs.selected_members.count(it.first) == 0) {
del_list.push_back(it.first);
continue;
}
std::vector<RTLIL::IdString> del_list2;
for (auto &it2 : it.second)
if (!rhs.selected_member(it.first, it2))
if (rhs.selected_members.at(it.first).count(it2) == 0)
del_list2.push_back(it2);
for (auto &it2 : del_list2)
it.second.erase(it2);
@ -668,7 +610,9 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se
return;
if (sel.full_selection) {
sel.clear();
sel.full_selection = false;
sel.selected_modules.clear();
sel.selected_members.clear();
sel.selected_modules.insert(design->selected_active_module);
return;
}
@ -701,7 +645,8 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
if (arg[0] == '%') {
if (arg == "%") {
work_stack.push_back(design->selection());
if (design->selection_stack.size() > 0)
work_stack.push_back(design->selection_stack.back());
} else
if (arg == "%%") {
while (work_stack.size() > 1) {
@ -851,16 +796,15 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
}
}
bool full_selection = (arg == "*" && arg_mod == "*");
work_stack.push_back(RTLIL::Selection(full_selection, select_blackboxes, design));
work_stack.push_back(RTLIL::Selection());
RTLIL::Selection &sel = work_stack.back();
if (sel.full_selection) {
if (sel.selects_boxes) sel.optimize(design);
if (arg == "*" && arg_mod == "*" && select_blackboxes) {
select_filter_active_mod(design, work_stack.back());
return;
}
sel.full_selection = false;
for (auto mod : design->modules())
{
if (!select_blackboxes && mod->get_blackbox_attribute())
@ -1001,33 +945,38 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
for (auto &it : arg_mod_found) {
if (it.second == false && !disable_empty_warning) {
std::string selection_str = select_blackboxes ? "=" : "";
selection_str += it.first;
log_warning("Selection \"%s\" did not match any module.\n", selection_str.c_str());
log_warning("Selection \"%s\" did not match any module.\n", it.first.c_str());
}
}
for (auto &it : arg_memb_found) {
if (it.second == false && !disable_empty_warning) {
std::string selection_str = select_blackboxes ? "=" : "";
selection_str += it.first;
log_warning("Selection \"%s\" did not match any object.\n", selection_str.c_str());
log_warning("Selection \"%s\" did not match any object.\n", it.first.c_str());
}
}
}
static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::Selection *sel, bool whole_modules = false)
{
bool push_selection = &design->selection() != sel;
if (push_selection) design->push_selection(*sel);
std::string desc = "Selection contains:\n";
for (auto mod : design->all_selected_modules())
for (auto mod : design->modules())
{
if (whole_modules && sel->selected_whole_module(mod->name))
desc += stringf("%s\n", id2cstr(mod->name));
for (auto it : mod->selected_members())
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it->name));
if (sel->selected_module(mod->name)) {
if (whole_modules && sel->selected_whole_module(mod->name))
desc += stringf("%s\n", id2cstr(mod->name));
for (auto wire : mod->wires())
if (sel->selected_member(mod->name, wire->name))
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(wire->name));
for (auto &it : mod->memories)
if (sel->selected_member(mod->name, it.first))
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it.first));
for (auto cell : mod->cells())
if (sel->selected_member(mod->name, cell->name))
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(cell->name));
for (auto &it : mod->processes)
if (sel->selected_member(mod->name, it.first))
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it.first));
}
}
if (push_selection) design->pop_selection();
return desc;
}
@ -1052,9 +1001,9 @@ void handle_extra_select_args(Pass *pass, const vector<string> &args, size_t arg
work_stack.pop_back();
}
if (work_stack.empty())
design->push_empty_selection();
design->selection_stack.push_back(RTLIL::Selection(false));
else
design->push_selection(work_stack.back());
design->selection_stack.push_back(work_stack.back());
}
// extern decl. in register.h
@ -1068,7 +1017,7 @@ RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *des
work_stack.pop_back();
}
if (work_stack.empty())
return RTLIL::Selection::EmptySelection(design);
return RTLIL::Selection(false);
return work_stack.back();
}
@ -1441,7 +1390,7 @@ struct SelectPass : public Pass {
if (f.fail())
log_error("Can't open '%s' for reading: %s\n", read_file.c_str(), strerror(errno));
auto sel = RTLIL::Selection::EmptySelection(design);
RTLIL::Selection sel(false);
string line;
while (std::getline(f, line)) {
@ -1482,7 +1431,7 @@ struct SelectPass : public Pass {
log_cmd_error("Option -unset can not be combined with -list, -write, -count, -set, %s.\n", common_flagset);
if (work_stack.size() == 0 && got_module) {
auto sel = RTLIL::Selection::FullSelection(design);
RTLIL::Selection sel;
select_filter_active_mod(design, sel);
work_stack.push_back(sel);
}
@ -1492,16 +1441,16 @@ struct SelectPass : public Pass {
work_stack.pop_back();
}
log_assert(!design->selection_stack.empty());
log_assert(design->selection_stack.size() > 0);
if (clear_mode) {
design->selection() = RTLIL::Selection::FullSelection(design);
design->selection_stack.back() = RTLIL::Selection(true);
design->selected_active_module = std::string();
return;
}
if (none_mode) {
design->selection() = RTLIL::Selection::EmptySelection(design);
design->selection_stack.back() = RTLIL::Selection(false);
return;
}
@ -1516,17 +1465,28 @@ struct SelectPass : public Pass {
if (f == nullptr)
log_error("Can't open '%s' for writing: %s\n", write_file.c_str(), strerror(errno));
}
RTLIL::Selection *sel = &design->selection_stack.back();
if (work_stack.size() > 0)
design->push_selection(work_stack.back());
RTLIL::Selection *sel = &design->selection();
sel = &work_stack.back();
sel->optimize(design);
for (auto mod : design->all_selected_modules())
for (auto mod : design->modules())
{
if (sel->selected_whole_module(mod->name) && list_mode)
log("%s\n", id2cstr(mod->name));
if (!list_mod_mode)
for (auto it : mod->selected_members())
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it->name))
if (sel->selected_module(mod->name) && !list_mod_mode) {
for (auto wire : mod->wires())
if (sel->selected_member(mod->name, wire->name))
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(wire->name))
for (auto &it : mod->memories)
if (sel->selected_member(mod->name, it.first))
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it.first))
for (auto cell : mod->cells())
if (sel->selected_member(mod->name, cell->name))
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(cell->name))
for (auto &it : mod->processes)
if (sel->selected_member(mod->name, it.first))
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it.first))
}
}
if (count_mode)
{
@ -1535,8 +1495,6 @@ struct SelectPass : public Pass {
}
if (f != nullptr)
fclose(f);
if (work_stack.size() > 0)
design->pop_selection();
#undef LOG_OBJECT
return;
}
@ -1545,8 +1503,8 @@ struct SelectPass : public Pass {
{
if (work_stack.size() == 0)
log_cmd_error("Nothing to add to selection.\n");
select_op_union(design, design->selection(), work_stack.back());
design->selection().optimize(design);
select_op_union(design, design->selection_stack.back(), work_stack.back());
design->selection_stack.back().optimize(design);
return;
}
@ -1554,8 +1512,8 @@ struct SelectPass : public Pass {
{
if (work_stack.size() == 0)
log_cmd_error("Nothing to delete from selection.\n");
select_op_diff(design, design->selection(), work_stack.back());
design->selection().optimize(design);
select_op_diff(design, design->selection_stack.back(), work_stack.back());
design->selection_stack.back().optimize(design);
return;
}
@ -1595,13 +1553,23 @@ struct SelectPass : public Pass {
if (work_stack.size() == 0)
log_cmd_error("No selection to check.\n");
RTLIL::Selection *sel = &work_stack.back();
design->push_selection(*sel);
sel->optimize(design);
for (auto mod : design->all_selected_modules()) {
module_count++;
for ([[maybe_unused]] auto member_name : mod->selected_members())
total_count++;
}
for (auto mod : design->modules())
if (sel->selected_module(mod->name)) {
module_count++;
for (auto wire : mod->wires())
if (sel->selected_member(mod->name, wire->name))
total_count++;
for (auto &it : mod->memories)
if (sel->selected_member(mod->name, it.first))
total_count++;
for (auto cell : mod->cells())
if (sel->selected_member(mod->name, cell->name))
total_count++;
for (auto &it : mod->processes)
if (sel->selected_member(mod->name, it.first))
total_count++;
}
if (assert_modcount >= 0 && assert_modcount != module_count)
{
log_error("Assertion failed: selection contains %d modules instead of the asserted %d:%s\n",
@ -1625,14 +1593,13 @@ struct SelectPass : public Pass {
log_error("Assertion failed: selection contains %d elements, less than the minimum number %d:%s\n%s",
total_count, assert_min, sel_str.c_str(), desc.c_str());
}
design->pop_selection();
return;
}
if (!set_name.empty())
{
if (work_stack.size() == 0)
design->selection_vars[set_name] = RTLIL::Selection::EmptySelection(design);
design->selection_vars[set_name] = RTLIL::Selection(false);
else
design->selection_vars[set_name] = work_stack.back();
return;
@ -1646,7 +1613,7 @@ struct SelectPass : public Pass {
}
if (work_stack.size() == 0) {
RTLIL::Selection &sel = design->selection();
RTLIL::Selection &sel = design->selection_stack.back();
if (sel.full_selection)
log("*\n");
for (auto &it : sel.selected_modules)
@ -1657,8 +1624,8 @@ struct SelectPass : public Pass {
return;
}
design->selection() = work_stack.back();
design->selection().optimize(design);
design->selection_stack.back() = work_stack.back();
design->selection_stack.back().optimize(design);
}
} SelectPass;
@ -1698,8 +1665,7 @@ struct CdPass : public Pass {
log_cmd_error("Invalid number of arguments.\n");
if (args.size() == 1 || args[1] == "/") {
design->pop_selection();
design->push_full_selection();
design->selection_stack.back() = RTLIL::Selection(true);
design->selected_active_module = std::string();
return;
}
@ -1708,8 +1674,7 @@ struct CdPass : public Pass {
{
string modname = design->selected_active_module;
design->pop_selection();
design->push_full_selection();
design->selection_stack.back() = RTLIL::Selection(true);
design->selected_active_module = std::string();
while (1)
@ -1726,10 +1691,9 @@ struct CdPass : public Pass {
continue;
design->selected_active_module = modname;
design->pop_selection();
design->push_full_selection();
select_filter_active_mod(design, design->selection());
design->selection().optimize(design);
design->selection_stack.back() = RTLIL::Selection();
select_filter_active_mod(design, design->selection_stack.back());
design->selection_stack.back().optimize(design);
return;
}
@ -1746,10 +1710,9 @@ struct CdPass : public Pass {
if (design->module(modname) != nullptr) {
design->selected_active_module = modname;
design->pop_selection();
design->push_full_selection();
select_filter_active_mod(design, design->selection());
design->selection().optimize(design);
design->selection_stack.back() = RTLIL::Selection();
select_filter_active_mod(design, design->selection_stack.back());
design->selection_stack.back().optimize(design);
return;
}
@ -1796,7 +1759,7 @@ struct LsPass : public Pass {
{
std::vector<IdString> matches;
for (auto mod : design->all_selected_modules())
for (auto mod : design->selected_modules())
matches.push_back(mod->name);
if (!matches.empty()) {