mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-31 00:13:18 +00:00
Code Activity

Revert "Refactor full_selection"

Browse source
This commit is contained in:
Miodrag Milanović 2025-04-07 12:11:55 +02:00 • committed by GitHub
parent 98d4355b82
commit d49364d96f
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
38 changed files with 270 additions and 707 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/cmds/design.cc
View file

@ -216,8 +216,8 @@ struct DesignPass : public Pass {
RTLIL::Selection sel;
if (argidx != args.size()) {
handle_extra_select_args(this, args, argidx, args.size(), copy_from_design);
sel = copy_from_design->selection();
copy_from_design->pop_selection();
sel = copy_from_design->selection_stack.back();
copy_from_design->selection_stack.pop_back();
argidx = args.size();
}
@ -368,7 +368,7 @@ struct DesignPass : public Pass {
design->selection_vars.clear();
design->selected_active_module.clear();
design->push_full_selection();
design->selection_stack.push_back(RTLIL::Selection());
}
if (reset_mode || reset_vlog_mode || !load_name.empty() || push_mode || pop_mode)