mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-31 00:13:18 +00:00
Code Activity

Revert "Refactor full_selection"

Browse source
This commit is contained in:
Miodrag Milanović 2025-04-07 12:11:55 +02:00 • committed by GitHub
parent 98d4355b82
commit d49364d96f
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
38 changed files with 270 additions and 707 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/add.cc
View file

@ -102,7 +102,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
RTLIL::Module *mod = design->module(cell->type);
if (mod == nullptr)
continue;
if (!mod->is_selected_whole())
if (!design->selected_whole_module(mod->name))
continue;
if (mod->get_blackbox_attribute())
continue;