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xilinx: Initial support for LUT4 devices.

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Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.

Fixes #1547
This commit is contained in:
Marcin Kościelnicki 2020-02-03 16:19:24 +01:00 • committed by Marcelina Kościelnicka
parent 1f54b0008f
commit d48950d92d
6 changed files with 235 additions and 54 deletions
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19
tests/arch/xilinx/fsm.ys
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@ -3,6 +3,8 @@ hierarchy -top fsm
proc
flatten
design -save orig
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
@ -17,3 +19,20 @@ select -assert-count 1 t:LUT2
select -assert-count 3 t:LUT5
select -assert-count 1 t:LUT6
select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
design -load orig
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 3 t:LUT3
select -assert-count 6 t:LUT4
select -assert-count 6 t:MUXF5
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D