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xilinx: Initial support for LUT4 devices.

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Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.

Fixes #1547
This commit is contained in:
Marcin Kościelnicki 2020-02-03 16:19:24 +01:00 • committed by Marcelina Kościelnicka
parent 1f54b0008f
commit d48950d92d
6 changed files with 235 additions and 54 deletions
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14
tests/arch/xilinx/add_sub.ys
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@ -1,11 +1,23 @@
read_verilog ../common/add_sub.v
hierarchy -top top
proc
design -save orig
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 16 t:LUT2
select -assert-count 8 t:LUT2
select -assert-count 2 t:CARRY4
select -assert-none t:LUT2 t:CARRY4 %% t:* %D
design -load orig
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 8 t:LUT2
select -assert-count 6 t:MUXCY
select -assert-count 8 t:XORCY
select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D