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Preserve VHDL architecture name in attribute

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This commit is contained in:
Miodrag Milanovic 2023-10-12 09:17:06 +02:00
parent 59fbee4009
commit d473a207a1
1 changed files with 8 additions and 0 deletions
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8
frontends/verific/verific.cc
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@ -52,6 +52,7 @@ USING_YOSYS_NAMESPACE
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT
#include "vhdl_file.h" #include "vhdl_file.h"
#include "VhdlUnits.h" #include "VhdlUnits.h"
#include "NameSpace.h"
#endif #endif
#ifdef VERIFIC_EDIF_SUPPORT #ifdef VERIFIC_EDIF_SUPPORT
@ -1276,6 +1277,13 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
} }
import_attributes(module->attributes, nl, nl); import_attributes(module->attributes, nl, nl);
module->set_string_attribute(ID::hdlname, nl->CellBaseName()); module->set_string_attribute(ID::hdlname, nl->CellBaseName());
#ifdef VERIFIC_VHDL_SUPPORT
if (nl->IsFromVhdl()) {
NameSpace name_space(0);
char *architecture_name = name_space.ReName(nl->Name()) ;
module->set_string_attribute(ID(architecture), (architecture_name) ? architecture_name : nl->Name());
}
#endif
const char *param_name ; const char *param_name ;
const char *param_value ; const char *param_value ;
MapIter mi; MapIter mi;