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ecp5 to use -max_iter 1
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@ -13,7 +13,7 @@ module TRELLIS_DPR16X4 (
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parameter [63:0] INITVAL = 64'h0000000000000000;
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parameter [63:0] INITVAL = 64'h0000000000000000;
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wire [3:0] \$DO ;
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wire [3:0] \$DO ;
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\$__ABC_DPR16X4_SEQ #(
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TRELLIS_DPR16X4 #(
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.WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
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.WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
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) _TECHMAP_REPLACE_ (
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) _TECHMAP_REPLACE_ (
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.DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
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.DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
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@ -113,7 +113,7 @@ module TRELLIS_DPR16X4 (
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input WRE,
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input WRE,
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input WCK,
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input WCK,
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input [3:0] RAD,
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input [3:0] RAD,
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output [3:0] DO
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/* (* abc_arrival=<TODO> *) */ output [3:0] DO
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);
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);
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parameter WCKMUX = "WCK";
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parameter WCKMUX = "WCK";
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parameter WREMUX = "WRE";
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parameter WREMUX = "WRE";
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@ -280,11 +280,10 @@ struct SynthEcp5Pass : public ScriptPass
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}
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}
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std::string techmap_args = "-map +/ecp5/latches_map.v";
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std::string techmap_args = "-map +/ecp5/latches_map.v";
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if (abc9)
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if (abc9)
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techmap_args += " -map +/ecp5/abc_map.v";
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techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
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run("techmap " + techmap_args);
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run("techmap " + techmap_args);
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if (abc9) {
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if (abc9) {
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run("read_verilog -icells -lib +/ecp5/abc_model.v");
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if (nowidelut)
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if (nowidelut)
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run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
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run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
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else
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else
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