From d46dc9c5b4362c1e333979cbbac4f3567904fee5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:18:36 -0700
Subject: [PATCH] ecp5 to use -max_iter 1
---
techlibs/ecp5/abc_map.v | 2 +-
techlibs/ecp5/cells_sim.v | 2 +-
techlibs/ecp5/synth_ecp5.cc | 3 +--
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
index e8187ed18..ffd25f06d 100644
--- a/techlibs/ecp5/abc_map.v
+++ b/techlibs/ecp5/abc_map.v
@@ -13,7 +13,7 @@ module TRELLIS_DPR16X4 (
parameter [63:0] INITVAL = 64'h0000000000000000;
wire [3:0] \$DO ;
- \$__ABC_DPR16X4_SEQ #(
+ TRELLIS_DPR16X4 #(
.WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
) _TECHMAP_REPLACE_ (
.DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index f79a27312..24de0c3c2 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -113,7 +113,7 @@ module TRELLIS_DPR16X4 (
input WRE,
input WCK,
input [3:0] RAD,
- output [3:0] DO
+ /* (* abc_arrival=<TODO> *) */ output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 93e1cd5b5..b1d3160ba 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -280,11 +280,10 @@ struct SynthEcp5Pass : public ScriptPass
}
std::string techmap_args = "-map +/ecp5/latches_map.v";
if (abc9)
- techmap_args += " -map +/ecp5/abc_map.v";
+ techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
run("techmap " + techmap_args);
if (abc9) {
- run("read_verilog -icells -lib +/ecp5/abc_model.v");
if (nowidelut)
run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
else