mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-24 06:43:41 +00:00
Code Activity

Added "$fa" cell type

Browse source
This commit is contained in:
Clifford Wolf 2014-09-08 12:15:39 +02:00
parent 1a88e47396
commit d46bac3305
8 changed files with 164 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

25
kernel/consteval.h
View file

@ -155,6 +155,31 @@ struct ConstEval
else
set(sig_y, y_values.front());
}
else if (cell->type == "$fa")
{
RTLIL::SigSpec sig_c = cell->getPort("\\C");
RTLIL::SigSpec sig_x = cell->getPort("\\X");
int width = SIZE(sig_c);
if (!eval(sig_a, undef, cell))
return false;
if (!eval(sig_b, undef, cell))
return false;
if (!eval(sig_c, undef, cell))
return false;
RTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);
RTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);
RTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);
RTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);
RTLIL::Const val_x = const_or(t2, t3, false, false, width);
set(sig_y, val_y);
set(sig_x, val_x);
}
else if (cell->type == "$alu")
{
bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();