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Added design->select() api and use it in extract pass

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This commit is contained in:
Clifford Wolf 2013-03-03 20:53:24 +01:00
parent 40646d3516
commit d4680fd5a0
2 changed files with 13 additions and 2 deletions
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8
passes/extract/extract.cc
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@ -156,7 +156,7 @@ namespace
return true;
}
void replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
{
SigMap sigmap(needle);
SigSet<std::pair<std::string, int>> sig2port;
@ -202,6 +202,8 @@ namespace
haystack->cells.erase(haystack_cell->name);
delete haystack_cell;
}
return cell;
}
}
@ -451,7 +453,9 @@ struct ExtractPass : public Pass {
log(" %s:%s", it2.first.c_str(), it2.second.c_str());
log("\n");
}
replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result);
RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result);
design->select(haystack_map.at(result.haystackGraphId), new_cell);
log(" new cell: %s\n", id2cstr(new_cell->name));
}
}
}