mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 11:12:29 +00:00
Code Activity

Revisions (#4)

Browse source 
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
This commit is contained in:
Tony Min 2024-07-08 10:57:16 -04:00 • committed by GitHub
parent 6fe0e00050
commit d41688f7d7
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
44 changed files with 435 additions and 1118 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/arch/microchip/uram_sr.ys
View file

@ -16,7 +16,7 @@
read_verilog uram_sr.v
synth_microchip -top uram_sr -abc9 -family polarfire -noiopad
synth_microchip -top uram_sr -family polarfire -noiopad
select -assert-count 1 t:RAM64x12
select -assert-none t:RAM64x12 %% t:* %D