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Revisions (#4)

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* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
This commit is contained in:
Tony Min 2024-07-08 10:57:16 -04:00 • committed by GitHub
parent 6fe0e00050
commit d41688f7d7
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44 changed files with 435 additions and 1118 deletions
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12
tests/arch/microchip/ram_SDP.ys
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@ -15,10 +15,16 @@
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog ram_SDP.v
synth_microchip -top ram_SDP -abc9 -family polarfire -noiopad
synth_microchip -top ram_SDP -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-count 1 t:CFG1
select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
# very similar to ram_SDP.v, except read enable is always active
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp
chparam -set DATA_WIDTH 32 -set ADDRESS_WIDTH 8
synth_microchip -top sync_ram_sdp -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-none t:RAM1K20 %% t:* %D