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https://github.com/YosysHQ/yosys
synced 2025-04-24 01:25:33 +00:00
Revisions (#4)
* area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com>
This commit is contained in:
Tony Min
GitHub
parent
6fe0e00050
commit
d41688f7d7
44 changed files with 435 additions and 1118 deletions
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@ -51,7 +51,7 @@ module CFG1 (
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endspecify
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endmodule
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(* abc9_lut=2 *)
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(* abc9_lut=1 *)
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module CFG2 (
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output Y,
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input A,
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@ -65,7 +65,7 @@ module CFG2 (
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endspecify
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endmodule
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(* abc9_lut=3 *)
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(* abc9_lut=1 *)
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module CFG3 (
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output Y,
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input A,
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@ -81,7 +81,7 @@ module CFG3 (
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endspecify
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endmodule
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(* abc9_lut=3 *)
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(* abc9_lut=1 *)
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module CFG4 (
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output Y,
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input A,
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@ -291,13 +291,6 @@ module ARI1 (
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endspecify
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endmodule
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// module FCEND_BUFF
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// module FCINIT_BUFF
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// module FLASH_FREEZE
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// module OSCILLATOR
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// module SYSCTRL_RESET_STATUS
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// module LIVE_PROBE_FB
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(* blackbox *)
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module GCLKBUF (
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(* iopad_external_pin *)
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@ -320,28 +313,6 @@ module GCLKBUF_DIFF (
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);
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endmodule
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(* blackbox *)
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module GCLKBIBUF (
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input D,
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input E,
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input EN,
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(* iopad_external_pin *)
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inout PAD,
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(* clkbuf_driver *)
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output Y
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);
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endmodule
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// module DFN1
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// module DFN1C0
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// module DFN1E1
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// module DFN1E1C0
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// module DFN1E1P0
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// module DFN1P0
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// module DLN1
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// module DLN1C0
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// module DLN1P0
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module INV (
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input A,
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output Y
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@ -588,121 +559,6 @@ module TRIBUFF_DIFF (
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parameter IOSTD = "";
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endmodule
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// module DDR_IN
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// module DDR_OUT
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// module RAM1K18
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// module RAM64x18
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// module MACC
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(* blackbox *)
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module SYSRESET (
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(* iopad_external_pin *)
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input DEVRST_N,
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output POWER_ON_RESET_N);
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endmodule
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(* blackbox *)
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module XTLOSC (
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(* iopad_external_pin *)
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input XTL,
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output CLKOUT);
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parameter [1:0] MODE = 2'h3;
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parameter real FREQUENCY = 20.0;
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endmodule
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(* blackbox *)
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module RAM1K18 (
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input [13:0] A_ADDR,
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input [2:0] A_BLK,
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(* clkbuf_sink *)
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input A_CLK,
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input [17:0] A_DIN,
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output [17:0] A_DOUT,
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input [1:0] A_WEN,
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input [2:0] A_WIDTH,
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input A_WMODE,
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input A_ARST_N,
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input A_DOUT_LAT,
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input A_DOUT_ARST_N,
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(* clkbuf_sink *)
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input A_DOUT_CLK,
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input A_DOUT_EN,
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input A_DOUT_SRST_N,
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input [13:0] B_ADDR,
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input [2:0] B_BLK,
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(* clkbuf_sink *)
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input B_CLK,
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input [17:0] B_DIN,
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output [17:0] B_DOUT,
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input [1:0] B_WEN,
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input [2:0] B_WIDTH,
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input B_WMODE,
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input B_ARST_N,
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input B_DOUT_LAT,
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input B_DOUT_ARST_N,
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(* clkbuf_sink *)
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input B_DOUT_CLK,
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input B_DOUT_EN,
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input B_DOUT_SRST_N,
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input A_EN,
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input B_EN,
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input SII_LOCK,
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output BUSY);
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endmodule
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(* blackbox *)
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module RAM64x18 (
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input [9:0] A_ADDR,
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input [1:0] A_BLK,
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input [2:0] A_WIDTH,
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output [17:0] A_DOUT,
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input A_DOUT_ARST_N,
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(* clkbuf_sink *)
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input A_DOUT_CLK,
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input A_DOUT_EN,
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input A_DOUT_LAT,
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input A_DOUT_SRST_N,
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(* clkbuf_sink *)
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input A_ADDR_CLK,
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input A_ADDR_EN,
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input A_ADDR_LAT,
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input A_ADDR_SRST_N,
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input A_ADDR_ARST_N,
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input [9:0] B_ADDR,
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input [1:0] B_BLK,
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input [2:0] B_WIDTH,
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output [17:0] B_DOUT,
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input B_DOUT_ARST_N,
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(* clkbuf_sink *)
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input B_DOUT_CLK,
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input B_DOUT_EN,
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input B_DOUT_LAT,
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input B_DOUT_SRST_N,
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(* clkbuf_sink *)
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input B_ADDR_CLK,
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input B_ADDR_EN,
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input B_ADDR_LAT,
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input B_ADDR_SRST_N,
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input B_ADDR_ARST_N,
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input [9:0] C_ADDR,
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(* clkbuf_sink *)
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input C_CLK,
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input [17:0] C_DIN,
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input C_WEN,
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input [1:0] C_BLK,
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input [2:0] C_WIDTH,
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input A_EN,
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input B_EN,
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input C_EN,
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input SII_LOCK,
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output BUSY);
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endmodule
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(* blackbox *)
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module MACC_PA (
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input DOTP,
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@ -218,6 +218,7 @@ struct MicrochipDffOptPass : public Pass {
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worthy_post_ce = true;
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} else if (sig_CE.data != State::S1) {
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// Strange. Should not happen in a reasonable flow, so bail.
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log_assert(false); // This DFF is always off
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continue;
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} else {
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lut_d_post_ce = lut_d;
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@ -241,6 +242,7 @@ struct MicrochipDffOptPass : public Pass {
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worthy_post_s = true;
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} else if (sig_S.data != (inv_s ? State::S1 : State::S0)) {
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// Strange. Should not happen in a reasonable flow, so bail.
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log_assert(false); // DFF is always in set mode
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continue;
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}
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}
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@ -263,6 +265,7 @@ struct MicrochipDffOptPass : public Pass {
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worthy_post_r = true;
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} else if (sig_R.data != (inv_r ? State::S1 : State::S0)) {
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// Strange. Should not happen in a reasonable flow, so bail.
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log_assert(false); // DFF is always in reset mode
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continue;
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}
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}
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@ -33,10 +33,8 @@ struct SynthMicrochipPass : public ScriptPass {
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log("\n");
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log(" synth_microchip [options]\n");
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log("\n");
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log("This command runs synthesis for Microchip FPGAs. Operating on\n");
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log("partly selected designs is not supported (you must submit a fully-selected \n");
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log("design). This command creates netlists that are compatible with Microchip \n");
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log("PolarFire devices.\n");
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log("This command runs synthesis for Microchip FPGAs. This command creates \n");
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log("netlists that are compatible with Microchip PolarFire devices. \n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as the top module\n");
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@ -55,6 +53,9 @@ struct SynthMicrochipPass : public ScriptPass {
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log(" Write the design to the specified BLIF file. Writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -vlog <file>\n");
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log(" write the design to the specified Verilog file. writing of an output\n");
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log(" file is omitted if this parameter is not specified.\n");
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log(" -nobram\n");
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log(" Do not use block RAM cells in output netlist\n");
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log("\n");
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@ -76,11 +77,8 @@ struct SynthMicrochipPass : public ScriptPass {
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log(" 'from_label' is synonymous to 'begin', and empty 'to_label' is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -flatten\n");
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log(" Flatten design before synthesis.\n");
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log("\n");
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log(" -flatten_before_abc\n");
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log(" Flatten design before abc tech mapping.\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -dff\n");
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log(" Run 'abc'/'abc9' with -dff option\n");
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@ -89,8 +87,8 @@ struct SynthMicrochipPass : public ScriptPass {
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log(" Run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
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log(" implies -dff.\n");
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log("\n");
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log(" -abc9\n");
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log(" Use new ABC9 flow (EXPERIMENTAL)\n");
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log(" -abc\n");
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log(" Use classic ABC flow instead of ABC9\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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@ -98,10 +96,9 @@ struct SynthMicrochipPass : public ScriptPass {
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log("\n");
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}
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std::string top_opt, edif_file, blif_file, family;
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std::string top_opt, edif_file, blif_file, vlog_file, family;
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bool flatten, retime, noiopad, noclkbuf, nobram, nocarry, nowidelut, nodsp;
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bool abc9, dff;
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bool flatten_before_abc;
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int lut_size;
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// debug dump switches
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@ -112,8 +109,9 @@ struct SynthMicrochipPass : public ScriptPass {
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top_opt = "-auto-top";
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edif_file.clear();
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blif_file.clear();
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vlog_file.clear();
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family = "polarfire";
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flatten = false;
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flatten = true;
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retime = false;
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noiopad = false;
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noclkbuf = false;
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@ -121,9 +119,8 @@ struct SynthMicrochipPass : public ScriptPass {
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nobram = false;
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nowidelut = false;
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nodsp = false;
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abc9 = false;
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abc9 = true;
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dff = false;
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flatten_before_abc = false;
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lut_size = 4;
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debug_memory = false;
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@ -153,6 +150,10 @@ struct SynthMicrochipPass : public ScriptPass {
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blif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-vlog" && argidx + 1 < args.size()) {
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vlog_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx + 1 < args.size()) {
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size_t pos = args[argidx + 1].find(':');
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if (pos == std::string::npos)
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@ -161,12 +162,8 @@ struct SynthMicrochipPass : public ScriptPass {
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run_to = args[argidx].substr(pos + 1);
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-flatten_before_abc") {
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flatten_before_abc = true;
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-retime") {
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@ -201,8 +198,8 @@ struct SynthMicrochipPass : public ScriptPass {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc9 = true;
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if (args[argidx] == "-abc") {
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abc9 = false;
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continue;
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}
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if (args[argidx] == "-nodsp") {
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@ -479,8 +476,6 @@ struct SynthMicrochipPass : public ScriptPass {
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if (check_label("map_luts")) {
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run("opt_expr -mux_undef -noclkinv");
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if (flatten_before_abc)
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run("flatten");
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if (help_mode)
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run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
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else if (abc9) {
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@ -535,6 +530,12 @@ struct SynthMicrochipPass : public ScriptPass {
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if (!blif_file.empty() || help_mode)
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run(stringf("write_blif %s", blif_file.c_str()));
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}
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if (check_label("vlog"))
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{
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if (!vlog_file.empty() || help_mode)
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run(stringf("write_verilog %s", help_mode ? "<file-name>" : vlog_file.c_str()));
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}
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}
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} SynthMicrochipPass;
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