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hierarchy: morphCell
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parent
6922a68cea
commit
d3d5738238
3 changed files with 37 additions and 20 deletions
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@ -327,17 +327,18 @@ struct IFExpander
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// something. or null otherwise (the module should be blackbox or we couldn't
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// find it and check is not set).
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RTLIL::Module *get_module(RTLIL::Design &design,
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RTLIL::Cell &cell,
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RTLIL::Cell *&cell,
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RTLIL::Module &parent,
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bool check,
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const std::vector<std::string> &libdirs)
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{
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std::string cell_type = cell.type.str();
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std::string cell_type = cell->type.str();
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RTLIL::Module *abs_mod = design.module("$abstract" + cell_type);
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if (abs_mod) {
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cell.type = abs_mod->derive(&design, cell_to_mod_params(cell.parameters));
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cell.parameters.clear();
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RTLIL::Module *mod = design.module(cell.type);
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auto new_cell_type = abs_mod->derive(&design, cell_to_mod_params(cell->parameters));
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cell->parameters.clear();
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cell = cell->module->morphCell(new_cell_type, cell);
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RTLIL::Module *mod = design.module(cell->type);
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log_assert(mod);
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return mod;
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}
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@ -356,12 +357,12 @@ RTLIL::Module *get_module(RTLIL::Design &design,
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};
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for (auto &ext : extensions_list) {
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std::string filename = dir + "/" + RTLIL::unescape_id(cell.type) + ext.first;
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std::string filename = dir + "/" + RTLIL::unescape_id(cell->type) + ext.first;
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if (!check_file_exists(filename))
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continue;
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Frontend::frontend_call(&design, NULL, filename, ext.second);
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RTLIL::Module *mod = design.module(cell.type);
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RTLIL::Module *mod = design.module(cell->type);
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if (!mod)
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log_error("File `%s' from libdir does not declare module `%s'.\n",
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filename.c_str(), cell_type.c_str());
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@ -372,7 +373,7 @@ RTLIL::Module *get_module(RTLIL::Design &design,
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// We couldn't find the module anywhere. Complain if check is set.
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if (check)
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log_error("Module `%s' referenced in module `%s' in cell `%s' is not part of the design.\n",
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cell_type.c_str(), parent.name.c_str(), cell.name.c_str());
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cell_type.c_str(), parent.name.c_str(), cell->name.c_str());
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return nullptr;
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}
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@ -479,7 +480,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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RTLIL::Module *mod = design->module(cell->type);
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if (!mod)
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{
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mod = get_module(*design, *cell, *module, flag_check || flag_simcheck || flag_smtcheck, libdirs);
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mod = get_module(*design, cell, *module, flag_check || flag_simcheck || flag_smtcheck, libdirs);
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// If we still don't have a module, treat the cell as a black box and skip
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// it. Otherwise, we either loaded or derived something so should set the
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@ -528,12 +529,16 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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continue;
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}
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cell->type = mod->derive(design,
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cell_to_mod_params(cell->parameters),
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if_expander.interfaces_to_add_to_submodule,
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if_expander.modports_used_in_submodule);
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cell->parameters.clear();
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did_something = true;
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{
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auto params = cell_to_mod_params(cell->parameters);
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cell->parameters.clear();
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auto type = mod->derive(design,
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params,
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if_expander.interfaces_to_add_to_submodule,
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if_expander.modports_used_in_submodule);
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cell = mod->morphCell(type, cell);
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did_something = true;
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}
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handle_interface_instance:
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