mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 02:45:52 +00:00
Code Activity

Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

Browse source 
added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc
This commit is contained in:
Ahmed Irfan 2014-09-22 11:35:04 +02:00
commit d3c67ad9b6
513 changed files with 34858 additions and 12079 deletions
Download patch file Download diff file Expand all files Collapse all files

4
backends/btor/verilog2btor.sh
View file

@ -17,14 +17,14 @@ FULL_PATH=$(readlink -f $1)
DIR=$(dirname $FULL_PATH)
./yosys -q -p "
read_verilog $1;
read_verilog -sv $1;
hierarchy -top $3;
hierarchy -libdir $DIR;
hierarchy -check;
proc;
opt; opt_const -mux_undef; opt;
rename -hide;;;
techmap -share_map pmux2mux.v;;
#techmap -share_map pmux2mux.v;;
splice; opt;
memory_dff -wr_only;
memory_collect;;