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https://github.com/YosysHQ/yosys
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More opt_muxtree cleanups
This commit is contained in:
Clifford Wolf
parent
0217ea0fb8
commit
d3b35017f8
1 changed files with 44 additions and 64 deletions
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@ -38,20 +38,18 @@ struct OptMuxtreeWorker
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int removed_count;
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struct bitinfo_t {
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int num;
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SigBit bit;
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bool seen_non_mux;
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vector<int> mux_users;
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vector<int> mux_drivers;
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pool<int> mux_users;
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pool<int> mux_drivers;
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};
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dict<SigBit, int> bit2num;
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idict<SigBit> bit2num;
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vector<bitinfo_t> bit2info;
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struct portinfo_t {
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int ctrl_sig;
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vector<int> input_sigs;
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vector<int> input_muxes;
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pool<int> input_sigs;
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pool<int> input_muxes;
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bool const_activated;
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bool const_deactivated;
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bool enabled;
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@ -93,14 +91,14 @@ struct OptMuxtreeWorker
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muxinfo_t muxinfo;
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muxinfo.cell = cell;
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for (int i = 0; i < sig_s.size(); i++) {
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RTLIL::SigSpec sig = sig_b.extract(i*sig_a.size(), sig_a.size());
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for (int i = 0; i < GetSize(sig_s); i++) {
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RTLIL::SigSpec sig = sig_b.extract(i*GetSize(sig_a), GetSize(sig_a));
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RTLIL::SigSpec ctrl_sig = assign_map(sig_s.extract(i, 1));
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portinfo_t portinfo;
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portinfo.ctrl_sig = sig2bits(ctrl_sig, false).front();
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for (int idx : sig2bits(sig)) {
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add_to_list(bit2info[idx].mux_users, mux2info.size());
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add_to_list(portinfo.input_sigs, idx);
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bit2info[idx].mux_users.insert(GetSize(mux2info));
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portinfo.input_sigs.insert(idx);
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}
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portinfo.const_activated = ctrl_sig.is_fully_const() && ctrl_sig.as_bool();
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portinfo.const_deactivated = ctrl_sig.is_fully_const() && !ctrl_sig.as_bool();
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@ -110,8 +108,8 @@ struct OptMuxtreeWorker
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portinfo_t portinfo;
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for (int idx : sig2bits(sig_a)) {
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add_to_list(bit2info[idx].mux_users, mux2info.size());
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add_to_list(portinfo.input_sigs, idx);
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bit2info[idx].mux_users.insert(GetSize(mux2info));
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portinfo.input_sigs.insert(idx);
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}
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portinfo.ctrl_sig = -1;
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portinfo.const_activated = false;
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@ -120,7 +118,7 @@ struct OptMuxtreeWorker
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muxinfo.ports.push_back(portinfo);
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for (int idx : sig2bits(sig_y))
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add_to_list(bit2info[idx].mux_drivers, mux2info.size());
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bit2info[idx].mux_drivers.insert(GetSize(mux2info));
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for (int idx : sig2bits(sig_s))
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bit2info[idx].seen_non_mux = true;
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@ -141,25 +139,25 @@ struct OptMuxtreeWorker
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bit2info[idx].seen_non_mux = true;
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}
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if (mux2info.size() == 0) {
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if (mux2info.empty()) {
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log(" No muxes found in this module.\n");
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return;
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}
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// Populate mux2info[].ports[]:
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// .input_muxes
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for (size_t i = 0; i < bit2info.size(); i++)
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for (int i = 0; i < GetSize(bit2info); i++)
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for (int j : bit2info[i].mux_users)
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for (auto &p : mux2info[j].ports) {
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if (is_in_list(p.input_sigs, i))
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if (p.input_sigs.count(i))
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for (int k : bit2info[i].mux_drivers)
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add_to_list(p.input_muxes, k);
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p.input_muxes.insert(k);
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}
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log(" Evaluating internal representation of mux trees.\n");
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dict<int, pool<int>> mux_to_users;
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root_muxes.resize(mux2info.size());
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root_muxes.resize(GetSize(mux2info));
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for (auto &bi : bit2info) {
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for (int i : bi.mux_drivers)
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@ -197,10 +195,10 @@ struct OptMuxtreeWorker
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}
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}
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if (live_ports.size() == mi.ports.size())
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if (GetSize(live_ports) == GetSize(mi.ports))
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continue;
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if (live_ports.size() == 0) {
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if (live_ports.empty()) {
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module->remove(mi.cell);
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continue;
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}
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@ -213,9 +211,9 @@ struct OptMuxtreeWorker
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RTLIL::SigSpec sig_ports = sig_b;
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sig_ports.append(sig_a);
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if (live_ports.size() == 1)
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if (GetSize(live_ports) == 1)
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{
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RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size());
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RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*GetSize(sig_a), GetSize(sig_a));
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module->connect(RTLIL::SigSig(sig_y, sig_in));
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module->remove(mi.cell);
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}
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@ -223,9 +221,9 @@ struct OptMuxtreeWorker
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{
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RTLIL::SigSpec new_sig_a, new_sig_b, new_sig_s;
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for (size_t i = 0; i < live_ports.size(); i++) {
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RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.size(), sig_a.size());
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if (i == live_ports.size()-1) {
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for (int i = 0; i < GetSize(live_ports); i++) {
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RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*GetSize(sig_a), GetSize(sig_a));
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if (i == GetSize(live_ports)-1) {
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new_sig_a = sig_in;
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} else {
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new_sig_b.append(sig_in);
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@ -236,30 +234,16 @@ struct OptMuxtreeWorker
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mi.cell->setPort("\\A", new_sig_a);
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mi.cell->setPort("\\B", new_sig_b);
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mi.cell->setPort("\\S", new_sig_s);
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if (new_sig_s.size() == 1) {
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if (GetSize(new_sig_s) == 1) {
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mi.cell->type = "$mux";
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mi.cell->parameters.erase("\\S_WIDTH");
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} else {
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mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
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mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(GetSize(new_sig_s));
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}
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}
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}
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}
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bool is_in_list(const vector<int> &list, int value)
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{
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for (int v : list)
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if (v == value)
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return true;
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return false;
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}
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void add_to_list(vector<int> &list, int value)
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{
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if (!is_in_list(list, value))
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list.push_back(value);
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}
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vector<int> sig2bits(RTLIL::SigSpec sig, bool skip_non_wires = true)
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{
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vector<int> results;
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@ -268,13 +252,11 @@ struct OptMuxtreeWorker
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if (bit.wire != NULL) {
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if (bit2num.count(bit) == 0) {
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bitinfo_t info;
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info.num = bit2info.size();
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info.bit = bit;
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info.seen_non_mux = false;
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bit2num.expect(bit, GetSize(bit2info));
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bit2info.push_back(info);
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bit2num[info.bit] = info.num;
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}
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results.push_back(bit2num[bit]);
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results.push_back(bit2num.at(bit));
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} else if (!skip_non_wires)
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results.push_back(-1);
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return results;
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@ -311,7 +293,7 @@ struct OptMuxtreeWorker
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knowledge.known_inactive.at(muxinfo.ports[i].ctrl_sig)++;
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}
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if (port_idx < int(muxinfo.ports.size())-1 && !muxinfo.ports[port_idx].const_activated)
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if (port_idx < GetSize(muxinfo.ports)-1 && !muxinfo.ports[port_idx].const_activated)
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knowledge.known_active.at(muxinfo.ports[port_idx].ctrl_sig)++;
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vector<int> parent_muxes;
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@ -327,11 +309,11 @@ struct OptMuxtreeWorker
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for (int m : parent_muxes)
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knowledge.visited_muxes[m] = false;
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if (port_idx < int(muxinfo.ports.size())-1 && !muxinfo.ports[port_idx].const_activated)
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if (port_idx < GetSize(muxinfo.ports)-1 && !muxinfo.ports[port_idx].const_activated)
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knowledge.known_active.at(muxinfo.ports[port_idx].ctrl_sig)--;
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for (size_t i = 0; i < muxinfo.ports.size(); i++) {
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if (int(i) == port_idx)
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for (int i = 0; i < GetSize(muxinfo.ports); i++) {
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if (i == port_idx)
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continue;
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if (muxinfo.ports[i].ctrl_sig >= 0)
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knowledge.known_inactive.at(muxinfo.ports[i].ctrl_sig)--;
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@ -373,7 +355,7 @@ struct OptMuxtreeWorker
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replace_known(knowledge, muxinfo, "\\B");
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// if there is a constant activated port we just use it
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for (size_t port_idx = 0; port_idx < muxinfo.ports.size()-1; port_idx++)
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for (int port_idx = 0; port_idx < GetSize(muxinfo.ports); port_idx++)
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{
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portinfo_t &portinfo = muxinfo.ports[port_idx];
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if (portinfo.const_activated) {
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@ -385,7 +367,7 @@ struct OptMuxtreeWorker
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// compare ports with known_active signals. if we find a match, only this
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// port can be active. do not include the last port (its the default port
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// that has no control signals).
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for (size_t port_idx = 0; port_idx < muxinfo.ports.size()-1; port_idx++)
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for (int port_idx = 0; port_idx < GetSize(muxinfo.ports)-1; port_idx++)
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{
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portinfo_t &portinfo = muxinfo.ports[port_idx];
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if (knowledge.known_active.at(portinfo.ctrl_sig)) {
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@ -398,11 +380,11 @@ struct OptMuxtreeWorker
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// signal of the port is known_inactive or if the control signals of all other
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// ports are known_active this port can't be activated. this loop includes the
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// default port but no known_inactive match is performed on the default port.
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for (size_t port_idx = 0; port_idx < muxinfo.ports.size(); port_idx++)
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for (int port_idx = 0; port_idx < GetSize(muxinfo.ports); port_idx++)
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{
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portinfo_t &portinfo = muxinfo.ports[port_idx];
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if (port_idx < muxinfo.ports.size()-1) {
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if (port_idx < GetSize(muxinfo.ports)-1) {
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bool found_non_known_inactive = false;
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if (knowledge.known_inactive.at(portinfo.ctrl_sig) == 0)
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found_non_known_inactive = true;
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@ -411,7 +393,7 @@ struct OptMuxtreeWorker
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}
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bool port_active = true;
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for (size_t i = 0; i < muxinfo.ports.size()-1; i++) {
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for (int i = 0; i < GetSize(muxinfo.ports)-1; i++) {
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if (i == port_idx)
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continue;
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if (knowledge.known_active.at(muxinfo.ports[i].ctrl_sig))
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@ -425,9 +407,9 @@ struct OptMuxtreeWorker
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void eval_root_mux(int mux_idx)
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{
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knowledge_t knowledge;
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knowledge.known_inactive.resize(bit2info.size());
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knowledge.known_active.resize(bit2info.size());
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knowledge.visited_muxes.resize(mux2info.size());
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knowledge.known_inactive.resize(GetSize(bit2info));
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knowledge.known_active.resize(GetSize(bit2info));
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knowledge.visited_muxes.resize(GetSize(mux2info));
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knowledge.visited_muxes[mux_idx] = true;
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eval_mux(knowledge, mux_idx);
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}
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@ -460,12 +442,10 @@ struct OptMuxtreePass : public Pass {
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log("Skipping module %s as it is only partially selected.\n", log_id(mod));
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continue;
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}
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if (mod->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", log_id(mod));
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} else {
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OptMuxtreeWorker worker(design, mod);
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total_count += worker.removed_count;
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}
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if (mod->has_processes_warn())
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continue;
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OptMuxtreeWorker worker(design, mod);
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total_count += worker.removed_count;
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}
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if (total_count)
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design->scratchpad_set_bool("opt.did_something", true);
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