mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

Removed alu and div_mod test as agreed, ignore generated files

Browse source
This commit is contained in:
Miodrag Milanovic 2019-10-04 08:24:37 +02:00
parent a7fbc8c3fe
commit d37cd267a5
5 changed files with 1 additions and 70 deletions
Download patch file Download diff file Expand all files Collapse all files

1
tests/xilinx/.gitignore vendored
View file

@ -2,3 +2,4 @@
/*.out
/run-test.mk
/*_uut.v
/test_macc

19
tests/xilinx/alu.v
View file

@ -1,19 +0,0 @@
module top (
input clock,
input [31:0] dinA, dinB,
input [2:0] opcode,
output reg [31:0] dout
);
always @(posedge clock) begin
case (opcode)
0: dout <= dinA + dinB;
1: dout <= dinA - dinB;
2: dout <= dinA >> dinB;
3: dout <= $signed(dinA) >>> dinB;
4: dout <= dinA << dinB;
5: dout <= dinA & dinB;
6: dout <= dinA | dinB;
7: dout <= dinA ^ dinB;
endcase
end
endmodule

21
tests/xilinx/alu.ys
View file

@ -1,21 +0,0 @@
read_verilog alu.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 32 t:LUT1
select -assert-count 142 t:LUT2
select -assert-count 55 t:LUT3
select -assert-count 70 t:LUT4
select -assert-count 46 t:LUT5
select -assert-count 625 t:LUT6
select -assert-count 62 t:MUXCY
select -assert-count 265 t:MUXF7
select -assert-count 79 t:MUXF8
select -assert-count 64 t:XORCY
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D

13
tests/xilinx/div_mod.v
View file

@ -1,13 +0,0 @@
module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x % y;
assign B = x / y;
endmodule

17
tests/xilinx/div_mod.ys
View file

@ -1,17 +0,0 @@
read_verilog div_mod.v
hierarchy -top top
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 12 t:LUT1
select -assert-count 19 t:LUT2
select -assert-count 13 t:LUT4
select -assert-count 6 t:LUT5
select -assert-count 82 t:LUT6
select -assert-count 65 t:MUXCY
select -assert-count 37 t:MUXF7
select -assert-count 11 t:MUXF8
select -assert-count 28 t:XORCY
select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D