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xilinx: Add SRLC16E primitive.

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Fixes #1331.
This commit is contained in:
Marcin Kościelnicki 2019-08-27 18:08:51 +02:00 • committed by Marcin Kościelnicki
parent eab3c1432b
commit d361f5ab79
1 changed files with 21 additions and 1 deletions
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22
techlibs/xilinx/cells_sim.v
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@ -394,7 +394,27 @@ module SRL16E (
always @(negedge CLK) if (CE) r <= { r[14:0], D }; always @(negedge CLK) if (CE) r <= { r[14:0], D };
end end
else else
always @(posedge CLK) if (CE) r <= { r[14:0], D }; always @(posedge CLK) if (CE) r <= { r[14:0], D };
endgenerate
endmodule
module SRLC16E (
output Q,
output Q15,
input A0, A1, A2, A3, CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
reg [15:0] r = INIT;
assign Q15 = r[15];
assign Q = r[{A3,A2,A1,A0}];
generate
if (IS_CLK_INVERTED) begin
always @(negedge CLK) if (CE) r <= { r[14:0], D };
end
else
always @(posedge CLK) if (CE) r <= { r[14:0], D };
endgenerate endgenerate
endmodule endmodule