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Add $dlatchsr support to clk2fflogic

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This commit is contained in:
Clifford Wolf 2018-02-26 12:20:28 +01:00
parent 675dd5347a
commit d31584c649
1 changed files with 25 additions and 4 deletions
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23
passes/sat/clk2fflogic.cc
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@ -153,7 +153,7 @@ struct Clk2fflogicPass : public Pass {
cell->setPort("\\WR_DATA", wr_data_port); cell->setPort("\\WR_DATA", wr_data_port);
} }
if (cell->type.in("$dlatch")) if (cell->type.in("$dlatch", "$dlatchsr"))
{ {
bool enpol = cell->parameters["\\EN_POLARITY"].as_bool(); bool enpol = cell->parameters["\\EN_POLARITY"].as_bool();
@ -168,10 +168,31 @@ struct Clk2fflogicPass : public Pass {
Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q)); Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
module->addFf(NEW_ID, sig_q, past_q); module->addFf(NEW_ID, sig_q, past_q);
if (cell->type == "$dlatch")
{
if (enpol) if (enpol)
module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q); module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
else else
module->addMux(NEW_ID, sig_d, past_q, sig_en, sig_q); module->addMux(NEW_ID, sig_d, past_q, sig_en, sig_q);
}
else
{
SigSpec t;
if (enpol)
t = module->Mux(NEW_ID, past_q, sig_d, sig_en);
else
t = module->Mux(NEW_ID, sig_d, past_q, sig_en);
SigSpec s = cell->getPort("\\SET");
if (!cell->parameters["\\SET_POLARITY"].as_bool())
s = module->Not(NEW_ID, s);
t = module->Or(NEW_ID, t, s);
SigSpec c = cell->getPort("\\CLR");
if (cell->parameters["\\CLR_POLARITY"].as_bool())
c = module->Not(NEW_ID, c);
module->addAnd(NEW_ID, t, c, sig_q);
}
Const initval; Const initval;
bool assign_initval = false; bool assign_initval = false;