mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-13 01:16:16 +00:00
Code Activity

Do not collect disabled $memwr cells

Browse source
This commit is contained in:
Clifford Wolf 2015-07-06 13:28:00 +02:00
parent c4dde71dca
commit d2ff5d9994
1 changed files with 16 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

29
passes/memory/memory_collect.cc
View file

@ -110,21 +110,24 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
SigSpec data = sigmap(cell->getPort("\\DATA")); SigSpec data = sigmap(cell->getPort("\\DATA"));
SigSpec en = sigmap(cell->getPort("\\EN")); SigSpec en = sigmap(cell->getPort("\\EN"));
clk.extend_u0(1, false); if (!en.is_fully_zero())
clk_enable.extend_u0(1, false); {
clk_polarity.extend_u0(1, false); clk.extend_u0(1, false);
addr.extend_u0(addr_bits, false); clk_enable.extend_u0(1, false);
data.extend_u0(memory->width, false); clk_polarity.extend_u0(1, false);
en.extend_u0(memory->width, false); addr.extend_u0(addr_bits, false);
data.extend_u0(memory->width, false);
en.extend_u0(memory->width, false);
sig_wr_clk.append(clk); sig_wr_clk.append(clk);
sig_wr_clk_enable.append(clk_enable); sig_wr_clk_enable.append(clk_enable);
sig_wr_clk_polarity.append(clk_polarity); sig_wr_clk_polarity.append(clk_polarity);
sig_wr_addr.append(addr); sig_wr_addr.append(addr);
sig_wr_data.append(data); sig_wr_data.append(data);
sig_wr_en.append(en); sig_wr_en.append(en);
wr_ports++; wr_ports++;
}
continue; continue;
} }