mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-06 03:10:26 +00:00
Code Activity

Do not collect disabled $memwr cells

Browse source
This commit is contained in:
Clifford Wolf 2015-07-06 13:28:00 +02:00
parent c4dde71dca
commit d2ff5d9994
1 changed files with 16 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

3
passes/memory/memory_collect.cc
View file

@ -110,6 +110,8 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
SigSpec data = sigmap(cell->getPort("\\DATA")); SigSpec data = sigmap(cell->getPort("\\DATA"));
SigSpec en = sigmap(cell->getPort("\\EN")); SigSpec en = sigmap(cell->getPort("\\EN"));
if (!en.is_fully_zero())
{
clk.extend_u0(1, false); clk.extend_u0(1, false);
clk_enable.extend_u0(1, false); clk_enable.extend_u0(1, false);
clk_polarity.extend_u0(1, false); clk_polarity.extend_u0(1, false);
@ -125,6 +127,7 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
sig_wr_en.append(en); sig_wr_en.append(en);
wr_ports++; wr_ports++;
}
continue; continue;
} }