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Do not compute sign bit if result is zero

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This commit is contained in:
Eddie Hung 2019-07-31 16:04:19 -07:00
parent 60c4887d15
commit d2c33863d0
1 changed files with 2 additions and 1 deletions
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3
techlibs/common/mul2dsp.v
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@ -69,7 +69,6 @@ module \$mul (A, B, Y);
);
else if (A_SIGNED && (A_WIDTH > `DSP_A_MAXWIDTH || B_WIDTH > `DSP_B_MAXWIDTH)) begin
wire _;
assign Y[Y_WIDTH-1] = A[A_WIDTH-1] ^ B[B_WIDTH-1];
\$__mul #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
@ -81,6 +80,8 @@ module \$mul (A, B, Y);
.B(B),
.Y({_,Y[Y_WIDTH-2:0]})
);
// For non-zero results, recompute sign bit
assign Y[Y_WIDTH-1] = (|Y[Y_WIDTH-2:0]) & (A[A_WIDTH-1] ^ B[B_WIDTH-1]);
end
else
\$__mul #(