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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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44
techlibs/xilinx/xilinx_srl.pmg
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@ -18,22 +18,22 @@ match first
select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
filter !non_first_cells.count(first)
generate
SigSpec C = module->addWire(NEW_ID);
SigSpec D = module->addWire(NEW_ID);
SigSpec Q = module->addWire(NEW_ID);
SigSpec C = module->addWire(NEWER_ID);
SigSpec D = module->addWire(NEWER_ID);
SigSpec Q = module->addWire(NEWER_ID);
auto r = rng(8);
Cell* cell;
switch (r)
{
case 0:
case 1:
cell = module->addCell(NEW_ID, \FDRE);
cell = module->addCell(NEWER_ID, \FDRE);
cell->setPort(\C, C);
cell->setPort(\D, D);
cell->setPort(\Q, Q);
cell->setPort(\CE, module->addWire(NEW_ID));
cell->setPort(\CE, module->addWire(NEWER_ID));
if (r & 1)
cell->setPort(\R, module->addWire(NEW_ID));
cell->setPort(\R, module->addWire(NEWER_ID));
else {
if (rng(2) == 0)
cell->setPort(\R, State::S0);
@ -41,13 +41,13 @@ generate
break;
case 2:
case 3:
cell = module->addDffGate(NEW_ID, C, D, Q, r & 1);
cell = module->addDffGate(NEWER_ID, C, D, Q, r & 1);
break;
case 4:
case 5:
case 6:
case 7:
cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2);
cell = module->addDffeGate(NEWER_ID, C, module->addWire(NEWER_ID), D, Q, r & 1, r & 2);
break;
default: log_abort();
}
@ -143,9 +143,9 @@ match next
filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()
filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
generate
Cell *cell = module->addCell(NEW_ID, chain.back()->type);
Cell *cell = module->addCell(NEWER_ID, chain.back()->type);
cell->setPort(\C, chain.back()->getPort(\C));
cell->setPort(\D, module->addWire(NEW_ID));
cell->setPort(\D, module->addWire(NEWER_ID));
cell->setPort(\Q, chain.back()->getPort(\D));
if (cell->type == \FDRE) {
if (rng(2) == 0)
@ -191,7 +191,7 @@ match shiftx
filter param(shiftx, \A_WIDTH).as_int() >= minlen
generate
minlen = 3;
module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID));
module->addShiftx(NEWER_ID, module->addWire(NEWER_ID, rng(6)+minlen), module->addWire(NEWER_ID, 3), module->addWire(NEWER_ID));
endmatch
code shiftx_width
@ -207,28 +207,28 @@ match first
index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]
set slice idx
generate
SigSpec C = module->addWire(NEW_ID);
SigSpec C = module->addWire(NEWER_ID);
auto WIDTH = rng(3)+1;
SigSpec D = module->addWire(NEW_ID, WIDTH);
SigSpec Q = module->addWire(NEW_ID, WIDTH);
SigSpec D = module->addWire(NEWER_ID, WIDTH);
SigSpec Q = module->addWire(NEWER_ID, WIDTH);
auto r = rng(8);
Cell *cell = nullptr;
switch (r)
{
case 0:
case 1:
cell = module->addDff(NEW_ID, C, D, Q, r & 1);
cell = module->addDff(NEWER_ID, C, D, Q, r & 1);
break;
case 2:
case 3:
case 4:
case 5:
//cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4);
//cell = module->addDffe(NEWER_ID, C, module->addWire(NEWER_ID), D, Q, r & 1, r & 4);
//break;
case 6:
case 7:
WIDTH = 1;
cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1);
cell = module->addDffGate(NEWER_ID, C, D[0], Q[0], r & 1);
break;
default: log_abort();
}
@ -295,19 +295,19 @@ generate
back->connections_.at(\D)[slice] = port(back, \Q)[new_slice];
}
else {
auto D = module->addWire(NEW_ID, WIDTH);
auto D = module->addWire(NEWER_ID, WIDTH);
if (back->type == $dff)
module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
module->addDff(NEWER_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
else if (back->type == $dffe)
module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
module->addDffe(NEWER_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
else
log_abort();
}
}
else if (back->type.begins_with("$_DFF_")) {
Cell *cell = module->addCell(NEW_ID, back->type);
Cell *cell = module->addCell(NEWER_ID, back->type);
cell->setPort(\C, back->getPort(\C));
cell->setPort(\D, module->addWire(NEW_ID));
cell->setPort(\D, module->addWire(NEWER_ID));
cell->setPort(\Q, back->getPort(\D));
}
else