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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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14
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -323,28 +323,28 @@ unmap:
Cell *lut_cell = 0;
switch (GetSize(final_lut.second)) {
case 1:
lut_cell = module->addCell(NEW_ID, ID(LUT1));
lut_cell = module->addCell(NEWER_ID, ID(LUT1));
break;
case 2:
lut_cell = module->addCell(NEW_ID, ID(LUT2));
lut_cell = module->addCell(NEWER_ID, ID(LUT2));
break;
case 3:
lut_cell = module->addCell(NEW_ID, ID(LUT3));
lut_cell = module->addCell(NEWER_ID, ID(LUT3));
break;
case 4:
lut_cell = module->addCell(NEW_ID, ID(LUT4));
lut_cell = module->addCell(NEWER_ID, ID(LUT4));
break;
case 5:
lut_cell = module->addCell(NEW_ID, ID(LUT5));
lut_cell = module->addCell(NEWER_ID, ID(LUT5));
break;
case 6:
lut_cell = module->addCell(NEW_ID, ID(LUT6));
lut_cell = module->addCell(NEWER_ID, ID(LUT6));
break;
default:
log_assert(!"unknown lut size");
}
lut_cell->attributes = cell_d->attributes;
Wire *lut_out = module->addWire(NEW_ID);
Wire *lut_out = module->addWire(NEWER_ID);
lut_cell->setParam(ID::INIT, final_lut.first);
cell->setPort(ID::D, lut_out);
lut_cell->setPort(ID::O, lut_out);

42
techlibs/xilinx/xilinx_dsp.cc
View file

@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN
#include "techlibs/xilinx/xilinx_dsp_cascade_pm.h"
static Cell* addDsp(Module *module) {
Cell *cell = module->addCell(NEW_ID, ID(DSP48E1));
Cell *cell = module->addCell(NEWER_ID, ID(DSP48E1));
cell->setParam(ID(ACASCREG), 0);
cell->setParam(ID(ADREG), 0);
cell->setParam(ID(A_INPUT), Const("DIRECT"));
@ -114,7 +114,7 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
AB.append(A);
C.append(B);
if (GetSize(Y) < 13)
Y.append(module->addWire(NEW_ID, 13-GetSize(Y)));
Y.append(module->addWire(NEWER_ID, 13-GetSize(Y)));
else
log_assert(GetSize(Y) == 13);
P.append(Y.extract(0, 12));
@ -160,15 +160,15 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
else {
AB.append(Const(0, 12));
C.append(Const(0, 12));
P.append(module->addWire(NEW_ID, 12));
CARRYOUT.append(module->addWire(NEW_ID, 1));
P.append(module->addWire(NEWER_ID, 12));
CARRYOUT.append(module->addWire(NEWER_ID, 1));
}
}
else {
AB.append(Const(0, 24));
C.append(Const(0, 24));
P.append(module->addWire(NEW_ID, 24));
CARRYOUT.append(module->addWire(NEW_ID, 2));
P.append(module->addWire(NEWER_ID, 24));
CARRYOUT.append(module->addWire(NEWER_ID, 2));
}
log_assert(GetSize(AB) == 48);
log_assert(GetSize(C) == 48);
@ -202,11 +202,11 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
C.append(A);
AB.append(B);
if (GetSize(Y) < 25)
Y.append(module->addWire(NEW_ID, 25-GetSize(Y)));
Y.append(module->addWire(NEWER_ID, 25-GetSize(Y)));
else
log_assert(GetSize(Y) == 25);
P.append(Y.extract(0, 24));
CARRYOUT.append(module->addWire(NEW_ID)); // TWO24 uses every other bit
CARRYOUT.append(module->addWire(NEWER_ID)); // TWO24 uses every other bit
CARRYOUT.append(Y[24]);
};
auto g24 = [&f24,module](std::deque<Cell*> &simd24) {
@ -294,7 +294,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.ffAD->type.in(ID($dffe), ID($sdffe))) {
bool pol = st.ffAD->getParam(ID::EN_POLARITY).as_bool();
SigSpec S = st.ffAD->getPort(ID::EN);
cell->setPort(ID(CEAD), pol ? S : pm.module->Not(NEW_ID, S));
cell->setPort(ID(CEAD), pol ? S : pm.module->Not(NEWER_ID, S));
}
else
cell->setPort(ID(CEAD), State::S1);
@ -373,7 +373,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(ID::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEWER_ID, srst));
} else {
cell->setPort(rstport, State::S0);
}
@ -381,7 +381,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(ID::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce));
}
else
cell->setPort(ceport, State::S1);
@ -437,13 +437,13 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.ffM) {
SigSpec M; // unused
f(M, st.ffM, ID(CEM), ID(RSTM));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEWER_ID, GetSize(st.sigM)));
cell->setParam(ID(MREG), State::S1);
}
if (st.ffP) {
SigSpec P; // unused
f(P, st.ffP, ID(CEP), ID(RSTP));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEWER_ID, GetSize(st.sigP)));
cell->setParam(ID(PREG), State::S1);
}
@ -477,7 +477,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
SigSpec P = st.sigP;
if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
P.append(pm.module->addWire(NEWER_ID, 48-GetSize(P)));
cell->setPort(ID::P, P);
pm.blacklist(cell);
@ -560,7 +560,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(ID::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEWER_ID, srst));
} else {
cell->setPort(rstport, State::S0);
}
@ -568,7 +568,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(ID::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce));
}
else
cell->setPort(ceport, State::S1);
@ -620,13 +620,13 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (st.ffM) {
SigSpec M; // unused
f(M, st.ffM, ID(CEM), ID(RSTM));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEWER_ID, GetSize(st.sigM)));
cell->setParam(ID(MREG), State::S1);
}
if (st.ffP) {
SigSpec P; // unused
f(P, st.ffP, ID(CEP), ID(RSTP));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEWER_ID, GetSize(st.sigP)));
cell->setParam(ID(PREG), State::S1);
}
@ -655,7 +655,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
SigSpec P = st.sigP;
if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
P.append(pm.module->addWire(NEWER_ID, 48-GetSize(P)));
cell->setPort(ID::P, P);
pm.blacklist(cell);
@ -683,7 +683,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(ID::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEWER_ID, srst));
} else {
cell->setPort(rstport, State::S0);
}
@ -691,7 +691,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(ID::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEWER_ID, ce));
}
else
cell->setPort(ceport, State::S1);

6
techlibs/xilinx/xilinx_dsp_cascade.pmg
View file

@ -89,7 +89,7 @@ finally
if (i % MAX_DSP_CASCADE > 0) {
if (P >= 0) {
Wire *cascade = module->addWire(NEW_ID, 48);
Wire *cascade = module->addWire(NEWER_ID, 48);
dsp_pcin->setPort(ID(C), Const(0, 48));
dsp_pcin->setPort(ID(PCIN), cascade);
dsp->setPort(ID(PCOUT), cascade);
@ -117,7 +117,7 @@ finally
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
}
if (AREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 30);
Wire *cascade = module->addWire(NEWER_ID, 30);
dsp_pcin->setPort(ID(A), Const(0, 30));
dsp_pcin->setPort(ID(ACIN), cascade);
dsp->setPort(ID(ACOUT), cascade);
@ -131,7 +131,7 @@ finally
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
}
if (BREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 18);
Wire *cascade = module->addWire(NEWER_ID, 18);
if (dsp->type.in(\DSP48A, \DSP48A1)) {
// According to UG389 p9 [https://www.xilinx.com/support/documentation/user_guides/ug389.pdf]
// "The DSP48A1 component uses this input when cascading

4
techlibs/xilinx/xilinx_srl.cc
View file

@ -59,7 +59,7 @@ void run_fixed(xilinx_srl_pm &pm)
auto first_cell = ud.longest_chain.back();
auto last_cell = ud.longest_chain.front();
Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEWER_ID, ID($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
@ -134,7 +134,7 @@ void run_variable(xilinx_srl_pm &pm)
auto first_cell = ud.chain.back().first;
auto first_slice = ud.chain.back().second;
Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
Cell *c = pm.module->addCell(NEWER_ID, ID($__XILINX_SHREG_));
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {

44
techlibs/xilinx/xilinx_srl.pmg
View file

@ -18,22 +18,22 @@ match first
select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
filter !non_first_cells.count(first)
generate
SigSpec C = module->addWire(NEW_ID);
SigSpec D = module->addWire(NEW_ID);
SigSpec Q = module->addWire(NEW_ID);
SigSpec C = module->addWire(NEWER_ID);
SigSpec D = module->addWire(NEWER_ID);
SigSpec Q = module->addWire(NEWER_ID);
auto r = rng(8);
Cell* cell;
switch (r)
{
case 0:
case 1:
cell = module->addCell(NEW_ID, \FDRE);
cell = module->addCell(NEWER_ID, \FDRE);
cell->setPort(\C, C);
cell->setPort(\D, D);
cell->setPort(\Q, Q);
cell->setPort(\CE, module->addWire(NEW_ID));
cell->setPort(\CE, module->addWire(NEWER_ID));
if (r & 1)
cell->setPort(\R, module->addWire(NEW_ID));
cell->setPort(\R, module->addWire(NEWER_ID));
else {
if (rng(2) == 0)
cell->setPort(\R, State::S0);
@ -41,13 +41,13 @@ generate
break;
case 2:
case 3:
cell = module->addDffGate(NEW_ID, C, D, Q, r & 1);
cell = module->addDffGate(NEWER_ID, C, D, Q, r & 1);
break;
case 4:
case 5:
case 6:
case 7:
cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2);
cell = module->addDffeGate(NEWER_ID, C, module->addWire(NEWER_ID), D, Q, r & 1, r & 2);
break;
default: log_abort();
}
@ -143,9 +143,9 @@ match next
filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()
filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
generate
Cell *cell = module->addCell(NEW_ID, chain.back()->type);
Cell *cell = module->addCell(NEWER_ID, chain.back()->type);
cell->setPort(\C, chain.back()->getPort(\C));
cell->setPort(\D, module->addWire(NEW_ID));
cell->setPort(\D, module->addWire(NEWER_ID));
cell->setPort(\Q, chain.back()->getPort(\D));
if (cell->type == \FDRE) {
if (rng(2) == 0)
@ -191,7 +191,7 @@ match shiftx
filter param(shiftx, \A_WIDTH).as_int() >= minlen
generate
minlen = 3;
module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID));
module->addShiftx(NEWER_ID, module->addWire(NEWER_ID, rng(6)+minlen), module->addWire(NEWER_ID, 3), module->addWire(NEWER_ID));
endmatch
code shiftx_width
@ -207,28 +207,28 @@ match first
index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]
set slice idx
generate
SigSpec C = module->addWire(NEW_ID);
SigSpec C = module->addWire(NEWER_ID);
auto WIDTH = rng(3)+1;
SigSpec D = module->addWire(NEW_ID, WIDTH);
SigSpec Q = module->addWire(NEW_ID, WIDTH);
SigSpec D = module->addWire(NEWER_ID, WIDTH);
SigSpec Q = module->addWire(NEWER_ID, WIDTH);
auto r = rng(8);
Cell *cell = nullptr;
switch (r)
{
case 0:
case 1:
cell = module->addDff(NEW_ID, C, D, Q, r & 1);
cell = module->addDff(NEWER_ID, C, D, Q, r & 1);
break;
case 2:
case 3:
case 4:
case 5:
//cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4);
//cell = module->addDffe(NEWER_ID, C, module->addWire(NEWER_ID), D, Q, r & 1, r & 4);
//break;
case 6:
case 7:
WIDTH = 1;
cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1);
cell = module->addDffGate(NEWER_ID, C, D[0], Q[0], r & 1);
break;
default: log_abort();
}
@ -295,19 +295,19 @@ generate
back->connections_.at(\D)[slice] = port(back, \Q)[new_slice];
}
else {
auto D = module->addWire(NEW_ID, WIDTH);
auto D = module->addWire(NEWER_ID, WIDTH);
if (back->type == $dff)
module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
module->addDff(NEWER_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
else if (back->type == $dffe)
module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
module->addDffe(NEWER_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
else
log_abort();
}
}
else if (back->type.begins_with("$_DFF_")) {
Cell *cell = module->addCell(NEW_ID, back->type);
Cell *cell = module->addCell(NEWER_ID, back->type);
cell->setPort(\C, back->getPort(\C));
cell->setPort(\D, module->addWire(NEW_ID));
cell->setPort(\D, module->addWire(NEWER_ID));
cell->setPort(\Q, back->getPort(\D));
}
else