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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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48
passes/techmap/simplemap.cc
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@ -35,7 +35,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::Y, sig_y[i]);
@ -80,7 +80,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
log_assert(!gate_type.empty());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type);
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
@ -122,7 +122,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
while (sig_a.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
RTLIL::SigSpec sig_t = module->addWire(NEWER_ID, sig_a.size() / 2);
for (int i = 0; i < sig_a.size(); i += 2)
{
@ -131,7 +131,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
continue;
}
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type);
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_a[i+1]);
@ -143,8 +143,8 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
}
if (cell->type == ID($reduce_xnor)) {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::SigSpec sig_t = module->addWire(NEWER_ID);
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_t);
@ -163,7 +163,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
{
while (sig.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
RTLIL::SigSpec sig_t = module->addWire(NEWER_ID, sig.size() / 2);
for (int i = 0; i < sig.size(); i += 2)
{
@ -172,7 +172,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
continue;
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_OR_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig[i]);
gate->setPort(ID::B, sig[i+1]);
@ -201,7 +201,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
sig_y = sig_y.extract(0, 1);
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_NOT_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_y);
@ -230,7 +230,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == ID($logic_or)) gate_type = ID($_OR_);
log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEWER_ID, gate_type);
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a);
gate->setPort(ID::B, sig_b);
@ -245,20 +245,20 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
bool is_ne = cell->type.in(ID($ne), ID($nex));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
RTLIL::SigSpec xor_out = module->addWire(NEWER_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEWER_ID, sig_a, sig_b, xor_out, is_signed);
xor_cell->attributes[ID::src] = cell->attributes[ID::src];
simplemap_bitop(module, xor_cell);
module->remove(xor_cell);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEWER_ID);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEWER_ID, xor_out, reduce_out);
reduce_cell->attributes[ID::src] = cell->attributes[ID::src];
simplemap_reduce(module, reduce_cell);
module->remove(reduce_cell);
if (!is_ne) {
RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
RTLIL::Cell *not_cell = module->addLogicNot(NEWER_ID, reduce_out, sig_y);
not_cell->attributes[ID::src] = cell->attributes[ID::src];
simplemap_lognot(module, not_cell);
module->remove(not_cell);
@ -272,7 +272,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
@ -289,7 +289,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
@ -305,7 +305,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_TBUF_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::E, sig_e);
@ -320,10 +320,10 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
int width = GetSize(cell->getPort(ID::Y));
for (int idx = 0; idx < GetSize(sel); idx++) {
SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
SigSpec new_data = module->addWire(NEWER_ID, GetSize(data)/2);
for (int i = 0; i < GetSize(new_data); i += width) {
for (int k = 0; k < width; k++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, data[i*2+k]);
gate->setPort(ID::B, data[i*2+width+k]);
@ -344,9 +344,9 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int());
for (int idx = 0; GetSize(lut_data) > 1; idx++) {
SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
SigSpec new_lut_data = module->addWire(NEWER_ID, GetSize(lut_data)/2);
for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEWER_ID, ID($_MUX_));
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->setPort(ID::A, lut_data[i]);
gate->setPort(ID::B, lut_data[i+1]);
@ -383,10 +383,10 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
}
}
products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1);
products.append(GetSize(in) > 0 ? module->Eq(NEWER_ID, in, pat) : State::S1);
}
module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID, products));
module->connect(cell->getPort(ID::Y), module->ReduceOr(NEWER_ID, products));
}
void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)