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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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8
passes/techmap/hilomap.cc
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@ -36,16 +36,16 @@ void hilomap_worker(RTLIL::SigSpec &sig)
for (auto &bit : sig) {
if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi == RTLIL::State::Sm) {
last_hi = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
last_hi = module->addWire(NEWER_ID);
RTLIL::Cell *cell = module->addCell(NEWER_ID, RTLIL::escape_id(hicell_celltype));
cell->setPort(RTLIL::escape_id(hicell_portname), last_hi);
}
bit = last_hi;
}
if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
if (!singleton_mode || last_lo == RTLIL::State::Sm) {
last_lo = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
last_lo = module->addWire(NEWER_ID);
RTLIL::Cell *cell = module->addCell(NEWER_ID, RTLIL::escape_id(locell_celltype));
cell->setPort(RTLIL::escape_id(locell_portname), last_lo);
}
bit = last_lo;