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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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42
passes/techmap/dfflegalize.cc
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@ -280,7 +280,7 @@ struct DffLegalizePass : public Pass {
void emulate_split_init_arst(FfData &ff) {
ff.remove();
FfData ff_dff(ff.module, &initvals, NEW_ID);
FfData ff_dff(ff.module, &initvals, NEWER_ID);
ff_dff.width = ff.width;
ff_dff.has_aload = ff.has_aload;
ff_dff.sig_aload = ff.sig_aload;
@ -293,11 +293,11 @@ struct DffLegalizePass : public Pass {
ff_dff.has_ce = ff.has_ce;
ff_dff.sig_ce = ff.sig_ce;
ff_dff.pol_ce = ff.pol_ce;
ff_dff.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_dff.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_dff.val_init = ff.val_init;
ff_dff.is_fine = ff.is_fine;
FfData ff_adff(ff.module, &initvals, NEW_ID);
FfData ff_adff(ff.module, &initvals, NEWER_ID);
ff_adff.width = ff.width;
ff_adff.has_aload = ff.has_aload;
ff_adff.sig_aload = ff.sig_aload;
@ -310,7 +310,7 @@ struct DffLegalizePass : public Pass {
ff_adff.has_ce = ff.has_ce;
ff_adff.sig_ce = ff.sig_ce;
ff_adff.pol_ce = ff.pol_ce;
ff_adff.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_adff.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_adff.val_init = Const(State::Sx, ff.width);
ff_adff.has_arst = true;
ff_adff.sig_arst = ff.sig_arst;
@ -318,9 +318,9 @@ struct DffLegalizePass : public Pass {
ff_adff.val_arst = ff.val_arst;
ff_adff.is_fine = ff.is_fine;
FfData ff_sel(ff.module, &initvals, NEW_ID);
FfData ff_sel(ff.module, &initvals, NEWER_ID);
ff_sel.width = 1;
ff_sel.sig_q = ff.module->addWire(NEW_ID);
ff_sel.sig_q = ff.module->addWire(NEWER_ID);
ff_sel.has_arst = true;
ff_sel.sig_arst = ff.sig_arst;
ff_sel.pol_arst = ff.pol_arst;
@ -329,9 +329,9 @@ struct DffLegalizePass : public Pass {
ff_sel.is_fine = ff.is_fine;
if (ff.is_fine)
ff.module->addMuxGate(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMuxGate(NEWER_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
else
ff.module->addMux(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMux(NEWER_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
legalize_ff(ff_dff);
legalize_ff(ff_adff);
@ -386,7 +386,7 @@ struct DffLegalizePass : public Pass {
log_assert(ff.width == 1);
ff.remove();
FfData ff_clr(ff.module, &initvals, NEW_ID);
FfData ff_clr(ff.module, &initvals, NEWER_ID);
ff_clr.width = ff.width;
ff_clr.has_aload = ff.has_aload;
ff_clr.sig_aload = ff.sig_aload;
@ -403,11 +403,11 @@ struct DffLegalizePass : public Pass {
ff_clr.sig_arst = ff.sig_clr;
ff_clr.pol_arst = ff.pol_clr;
ff_clr.val_arst = Const(State::S0, ff.width);
ff_clr.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_clr.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_clr.val_init = init_clr ? ff.val_init : Const(State::Sx, ff.width);
ff_clr.is_fine = ff.is_fine;
FfData ff_set(ff.module, &initvals, NEW_ID);
FfData ff_set(ff.module, &initvals, NEWER_ID);
ff_set.width = ff.width;
ff_set.has_aload = ff.has_aload;
ff_set.sig_aload = ff.sig_aload;
@ -424,25 +424,25 @@ struct DffLegalizePass : public Pass {
ff_set.sig_arst = ff.sig_set;
ff_set.pol_arst = ff.pol_set;
ff_set.val_arst = Const(State::S1, ff.width);
ff_set.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_set.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_set.val_init = init_set ? ff.val_init : Const(State::Sx, ff.width);
ff_set.is_fine = ff.is_fine;
FfData ff_sel(ff.module, &initvals, NEW_ID);
FfData ff_sel(ff.module, &initvals, NEWER_ID);
ff_sel.width = ff.width;
ff_sel.has_sr = true;
ff_sel.pol_clr = ff.pol_clr;
ff_sel.pol_set = ff.pol_set;
ff_sel.sig_clr = ff.sig_clr;
ff_sel.sig_set = ff.sig_set;
ff_sel.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_sel.sig_q = ff.module->addWire(NEWER_ID, ff.width);
ff_sel.val_init = Const(initsel, ff.width);
ff_sel.is_fine = ff.is_fine;
if (!ff.is_fine)
ff.module->addMux(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMux(NEWER_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
else
ff.module->addMuxGate(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
ff.module->addMuxGate(NEWER_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
legalize_ff(ff_clr);
legalize_ff(ff_set);
@ -841,11 +841,11 @@ struct DffLegalizePass : public Pass {
ff.sig_ad = State::S0;
ff.val_arst = State::S1;
ff.remove_init();
Wire *new_q = ff.module->addWire(NEW_ID);
Wire *new_q = ff.module->addWire(NEWER_ID);
if (ff.is_fine)
ff.module->addNotGate(NEW_ID, new_q, ff.sig_q);
ff.module->addNotGate(NEWER_ID, new_q, ff.sig_q);
else
ff.module->addNot(NEW_ID, new_q, ff.sig_q);
ff.module->addNot(NEWER_ID, new_q, ff.sig_q);
ff.sig_q = new_q;
if (ff.val_init == State::S0)
ff.val_init = State::S1;
@ -938,9 +938,9 @@ struct DffLegalizePass : public Pass {
} else if (sig == State::S1) {
sig = State::S0;
} else if (ff.is_fine) {
sig = ff.module->NotGate(NEW_ID, sig);
sig = ff.module->NotGate(NEWER_ID, sig);
} else {
sig = ff.module->Not(NEW_ID, sig);
sig = ff.module->Not(NEWER_ID, sig);
}
pol = !pol;
}