mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-11 02:08:08 +00:00
Code Activity

s/NEW_ID/NEWER_ID/g

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/techmap/bufnorm.cc
View file

@ -384,7 +384,7 @@ struct BufnormPass : public Pass {
it->second.sort(compare_wires_f);
w = *(it->second.begin());
} else {
w = module->addWire(NEW_ID, GetSize(conn.second));
w = module->addWire(NEWER_ID, GetSize(conn.second));
for (int i = 0; i < GetSize(w); i++)
sigmap.add(SigBit(w, i), keysig[i]);
}
@ -434,7 +434,7 @@ struct BufnormPass : public Pass {
return;
}
Cell *cell = module->addCell(NEW_ID, type);
Cell *cell = module->addCell(NEWER_ID, type);
added_buffers.insert(cell);
cell->setPort(ID::A, src);