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s/NEW_ID/NEWER_ID/g

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This commit is contained in:
Emil J. Tywoniak 2025-09-16 17:43:02 +02:00
parent e4d4de1020
commit d2b28d7a25
130 changed files with 1275 additions and 1275 deletions
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6
passes/sat/freduce.cc
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@ -716,7 +716,7 @@ struct FreduceWorker
log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID);
RTLIL::Wire *dummy_wire = module->addWire(NEWER_ID);
for (auto &port : drv->connections_)
if (ct.cell_output(drv->type, port.first))
sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
@ -725,9 +725,9 @@ struct FreduceWorker
{
if (inv_sig.size() == 0)
{
inv_sig = module->addWire(NEW_ID);
inv_sig = module->addWire(NEWER_ID);
RTLIL::Cell *inv_cell = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *inv_cell = module->addCell(NEWER_ID, ID($_NOT_));
inv_cell->setPort(ID::A, grp[0].bit);
inv_cell->setPort(ID::Y, inv_sig);
}